ZedBoard

Overview

The Avnet ZedBoard (Zynq Evaluation and Development board) is a low-cost development board for the Xilinx Zynq-7000 All Programmable SoC. It is built around the XC7Z020 device, which combines a dual-core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic on a single die. The board is co-developed by Avnet, Digilent, Xilinx, and ARM.

Hardware

Supported Features

The zedboard board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`zedboard/xc7z020` target

On-target memory for this board target: 511 MiB of RAM, N/A of Flash.

Type	Location	Description	Compatible
CPU	on-board	ARM Cortex-A9 CPU2	`arm,cortex-a9`
Ethernet	on-chip	Xilinx GEM Ethernet controller1 1	`xlnx,gem`
	on-chip	Xilinx GEM MDIO node1 1	`xlnx,gem-mdio`
	on-board	Generic MII PHY1	`ethernet-phy`
GPIO & Headers	on-chip	Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO Controller1	`xlnx,ps-gpio`
GPIO & Headers	on-chip	Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO Controller bank4	`xlnx,ps-gpio-bank`
I2C	on-chip	Cadence I2C controller2	`cdns,i2c`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	ARM Generic Interrupt Controller v11	`arm,gic-v1`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
Pin control	on-chip	Xilinx Zynq-7000 SoC series pinctrl node1	`xlnx,pinctrl-zynq`
Serial controller	on-chip	Xilinx PS UART1 1	`xlnx,xuartps`
SPI	on-chip	Cadence SPI controller2	`cdns,spi`
SRAM	on-board	Generic on-chip SRAM1	`mmio-sram`
System controller	on-chip	System Controller Registers R/W1	`syscon`
Timer	on-chip	per-core ARM architected timer1	`arm,armv8-timer`

Programming and Debugging

The Zynq-7000 series SoC needs to be initialized prior to running a Zephyr application. This can be achieved in a number of ways (e.g. using the Xilinx First Stage Boot Loader (FSBL), the Xilinx Vivado generated ps_init.tcl JTAG script, Das U-Boot Secondary Program Loader (SPL), …).

The instructions here use the U-Boot SPL. For further details and instructions for using Das U-Boot with Xilinx Zynq-7000 series SoCs, see the following documentation:

Building Das U-Boot

Clone and build Das U-Boot for the Avnet ZedBoard:

git clone -b v2026.04 https://source.denx.de/u-boot/u-boot.git
cd u-boot
make distclean
make xilinx_zynq_virt_defconfig
export PATH=/path/to/zephyr-sdk/arm-zephyr-eabi/bin/:$PATH
export CROSS_COMPILE=arm-zephyr-eabi-
export DEVICE_TREE="zynq-zed"
make

Running an Application

Load and run a Zephyr application via U-Boot from an SD card. Build the Hello World application:

# From the root of the zephyr repository
west build -b zedboard samples/hello_world

Copy u-boot/spl/boot.bin, u-boot/u-boot.img, and build/zephyr/zephyr.bin to a FAT32 formatted microSD card, insert the card in the SD slot on the ZedBoard, ensure the board is configured for SD boot (set the JP7-JP11 jumpers accordingly), and turn on the board.

Once U-Boot is done initializing, load and run the Zephyr application. The caches are turned off because Zephyr expects to bring up the MMU and caches itself:

Zynq> fatload mmc 0 0x100000 zephyr.bin
Zynq> dcache off
Zynq> icache off
Zynq> go 0x100000
## Starting application at 0x00100000 ...
*** Booting Zephyr OS vx.xx.x-xxx-gxxxxxxxxxxxx ***
Hello World! zedboard

Note

Only SD-card boot via U-Boot has been verified on this board. JTAG-based west flash / west debug are not yet supported.