AMD Zynq UltraScale+ MPSoC APU

Board Overview

Name:

zynqmp_apu

Vendor:

Advanced Micro Devices (AMD), Inc.

Status:

Maintained

Architecture:

arm64

SoC:

zynqmp_apu

Browse board sources

Overview

This board targets the Cortex-A53 application processing unit (APU) on AMD Zynq UltraScale+ MPSoC devices. GIC-400 for the APU cluster is at 0xf9010000, high DDR at 0x8_0000_0000, and PS UART0 at 0xff000000.

Hardware

Supported Features

The zynqmp_apu board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

zynqmp_apu/zynqmp_apu target

On-target memory for this board target: 2 GiB of RAM, N/A of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A53 CPU1	arm,cortex-a53
Interrupt controller	on-chip	ARM Generic Interrupt Controller v21	arm,gic-v2
Power management CPU operations	on-chip	Power State Coordination Interface (PSCI) version 0.21	arm,psci-0.2
Serial controller	on-chip	Xilinx PS UART11	xlnx,xuartps
SRAM	on-board	Generic on-chip SRAM1	mmio-sram
Timer	on-chip	Xilinx PS Triple-Timer Counter4	xlnx,ttcps
	on-chip	per-core ARM architected timer1	arm,armv8-timer

zynqmp_apu/zynqmp_apu/smp target

On-target memory for this board target: 2 GiB of RAM, N/A of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A53 CPU4	arm,cortex-a53
Interrupt controller	on-chip	ARM Generic Interrupt Controller v21	arm,gic-v2
Power management CPU operations	on-chip	Power State Coordination Interface (PSCI) version 0.21	arm,psci-0.2
Serial controller	on-chip	Xilinx PS UART11	xlnx,xuartps
SRAM	on-board	Generic on-chip SRAM1	mmio-sram
Timer	on-chip	Xilinx PS Triple-Timer Counter4	xlnx,ttcps
	on-chip	per-core ARM architected timer1	arm,armv8-timer

The default console is UART0 (typical Linux name ttyPS0).

Memories

• sram0 uses the low DDR window (2 GiB from 0x0).

Known limitations

• Only CPU0 is supported by this configuration.

Programming and Debugging

The zynqmp_apu board supports the runners and associated west commands listed below.

	flash	debug	reset	attach	rtt	debugserver	robot	simulate
xsdb	✅ (default)	✅ (default)	✅	✅	✅	✅	✅	✅

Build (example):

# From the root of the zephyr repository
west build -b zynqmp_apu samples/hello_world

Arm Trusted Firmware (TF-A)

When CONFIG_BUILD_WITH_TFA is enabled (default for this board), the build also produces TF-A bl31.elf under build/tfa/zynqmp/<release|debug>/bl31/. On hardware, Zephyr runs as BL33 after platform firmware (bitstream, FSBL, and PMUFW from the PDI) and TF-A have initialized the PS and provide PSCI via SMC.

AMD ZynqMP boards do not boot from fip.bin. TF-A is built with PRELOADED_BL33_BASE set to the Zephyr load address from devicetree, and the XSDB runner loads the bitstream, FSBL, bl31.elf, and Zephyr ELF separately. When CONFIG_BUILD_WITH_TFA is enabled, west flash passes the built bl31.elf path automatically via --bl31.

References

1. AMD Zynq UltraScale+ Device Technical Reference Manual (UG1085)