AMD Zynq UltraScale+ MPSoC RPU

Board Overview

Name:

zynqmp_rpu

Vendor:

Advanced Micro Devices (AMD), Inc.

Status:

Maintained

Architecture:

arm

SoC:

zynqmp_rpu

Browse board sources

Overview

This board configuration targets the Cortex-R5 real-time processing unit (RPU) on AMD Zynq UltraScale+ MPSoC. R5 DDR starts at 0x00400000, GIC for the RPU is at 0xf9000000, and PS UART0 is at 0xff000000.

Hardware

Supported Features

The zynqmp_rpu board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

zynqmp_rpu/zynqmp_rpu target

On-target memory for this board target: 64 MiB of RAM, 512 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-R5F CPU1	arm,cortex-r5f
EDAC	on-chip	Xilinx ZynqMP DDR memory controller1	xlnx,zynqmp-ddrc-2.40a
Ethernet	on-chip	Xilinx GEM Ethernet controller4	xlnx,gem
	on-chip	Xilinx GEM MDIO node4	xlnx,gem-mdio
GPIO & Headers	on-chip	Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO Controller1	xlnx,ps-gpio
	on-chip	Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO Controller bank6	xlnx,ps-gpio-bank
I2C	on-chip	Cadence I2C controller2	cdns,i2c
Interrupt controller	on-chip	ARM Generic Interrupt Controller v11	arm,gic-v1
IPM	on-chip	The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents2	xlnx,zynqmp-ipi-mailbox
MTD	on-chip	Flash node1	soc-nv-flash
Pin control	on-chip	Xilinx ZynqMP SoC Pin Controller1	xlnx,pinctrl-zynqmp
Serial controller	on-chip	Xilinx PS UART11	xlnx,xuartps
SPI	on-chip	Cadence SPI controller2	cdns,spi
	on-chip	Xilinx ZynqMP Quad SPI interface1	xlnx,zynqmp-qspi-1.0
SRAM	on-board	Generic on-chip SRAM1	mmio-sram
Timer	on-chip	Xilinx PS Triple-Timer Counter13	xlnx,ttcps

The default console is UART0 (typical Linux name ttyPS0).

Memories

• sram0 is at 0x0400_0000 (64 MiB).

• QSPI linear flash is mapped at 0xc0000000 (512 MiB).

Known limitations

• Dual-redundant lock-step R5 operation is not targeted by this board file.

• Only the first R5 core is supported.

Programming and Debugging

The zynqmp_rpu board supports the runners and associated west commands listed below.

	flash	debug	reset	attach	rtt	debugserver	robot	simulate
xsdb	✅ (default)	✅ (default)	✅	✅	✅	✅	✅	✅

QEMU

The board uses the arm-generic-fdt QEMU machine with a ZCU102 hardware DTB compiled from zynqmp_rpu-qemu.dts at build time. The Zephyr ELF is loaded on cpu-num=4 (the R5 cluster); MMIO pokes at 0xff5e023c and 0xff9a0000 release the R5 from reset.

west build -b zynqmp_rpu samples/hello_world
west build -t run

Hardware (XSDB)

# From the root of the zephyr repository
west build -b zynqmp_rpu samples/hello_world

References

1. AMD Zynq UltraScale+ Device Technical Reference Manual (UG1085)