CY8CPROTO-062-4343W

Overview

The CY8CPROTO-062-4343W PSOC 6 Wi-Fi BT Prototyping Kit is a low-cost hardware platform that enables design and debug of PSOC 6 MCUs. It comes with a Murata LBEE5KL1DX module, based on the CYW4343W combo device, industry-leading CAPSENSE for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone, and a thermistor.

This kit is designed with a snap-away form-factor, allowing the user to separate the different components and features that come with this kit and use independently. In addition, support for Digilent’s Pmod interface is also provided with this kit.

Hardware

For more information about the PSOC 62 MCU SoC and CY8CPROTO-062-4343W board:

Kit Features:

  • Support of up to 2MB Flash and 1MB SRAM

  • Dedicated SDHC to interface with WICED wireless devices.

  • Delivers dual-cores, with a 150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm Cortex-M0+ as the secondary processor for low-power operations.

  • Supports Full-Speed USB, capacitive-sensing with CAPSENSE, a PDM-PCM digital microphone interface, a Quad-SPI interface, 13 serial communication blocks, 7 programmable analog blocks, and 56 programmable digital blocks.

Kit Contents:

  • PSOC 6 Wi-Fi BT Prototyping Board

  • USB Type-A to Micro-B cable

  • Quick start guide

Supported Features

The cy8cproto_062_4343w board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

cy8cproto_062_4343w/cy8c624abzi_s2d44 target

Type

Location

Description

Compatible

CPU

on-chip

ARM Cortex-M0+ CPU1

arm,cortex-m0+

on-chip

ARM Cortex-M4F CPU1

arm,cortex-m4f

ADC

on-chip

Infineon Cat1 ADC Each ADC group Cat1 is assigned to a Zephyr device1

infineon,cat1-adc

ARM architecture

on-chip

Infineon Serial Communication Blocks (SCB) node10

infineon,cat1-scb

Bluetooth

on-board

CYW43xxx Connectivity that uses Zephyr’s Bluetooth Host Controller Interface UART driver1

infineon,cyw43xxx-bt-hci

Clock control

on-chip

Generic fixed-rate clock provider2 1

fixed-clock

on-chip

Generic fixed factor clock provider6 7

fixed-factor-clock

Counter

on-chip

Infineon counters1 31

infineon,cat1-counter

DMA

on-chip

Infineon CAT1 DMA node2

infineon,cat1-dma

Flash controller

on-chip

Infineon CAT1 flash controller1

infineon,cat1-flash-controller

GPIO & Headers

on-chip

Infineon CAT1 GPIO Port8 7

infineon,cat1-gpio

I2C

on-chip

Infineon CAT1 I2C driver1

infineon,cat1-i2c

Input

on-board

Group of GPIO-bound input keys1

gpio-keys

Interrupt controller

on-chip

ARMv7-M NVIC (Nested Vectored Interrupt Controller)1

arm,v7m-nvic

LED

on-board

Group of GPIO-controlled LEDs1

gpio-leds

MTD

on-chip

Flash node2

soc-nv-flash

Pin control

on-chip

Infineon CAT1 Pinctrl Container1

infineon,cat1-pinctrl

SDHC

on-chip

Infineon CAT1 SDHC/SDIO controller1

infineon,cat1-sdhc-sdio

Serial controller

on-chip

Infineon CAT1 UART2

infineon,cat1-uart

SRAM

on-chip

Generic on-chip SRAM description1

mmio-sram

Timer

on-chip

ARMv7-M System Tick1

arm,armv7m-systick

Watchdog

on-chip

Infineon CAT1 Watchdog1

infineon,cat1-watchdog

Wi-Fi

on-board

AIROC Wi-Fi Connectivity over SPI1

infineon,airoc-wifi

System Clock

The PSOC 62 MCU SoC is configured to use the internal IMO+FLL as a source for the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the system clock are provided in the SOC, depending on your system requirements.

Fetch Binary Blobs

cy8cproto_062_4343w board optionally uses binary blobs for features (e.g WIFI/Bluetooth chip firmware, CM0p prebuilt images, etc).

To fetch Binary Blobs:

west blobs fetch hal_infineon

Build blinking led sample

Here is an example for building the Blinky sample application.

# From the root of the zephyr repository
west build -b cy8cproto_062_4343w samples/basic/blinky

Programming and Debugging

The CY8CPROTO-062-4343W includes an onboard programmer/debugger (KitProg3) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed.

Infineon OpenOCD Installation

Both the full ModusToolbox and the ModusToolbox Programming Tools packages include Infineon OpenOCD. Installing either of these packages will also install Infineon OpenOCD. If neither package is installed, a minimal installation can be done by downloading the Infineon OpenOCD release for your system and manually extract the files to a location of your choice.

Note

Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script openocd/udev_rules/install_rules.sh.

West Commands

The path to the installed Infineon OpenOCD executable must be available to the west tool commands. There are multiple ways of doing this. The example below uses a permanent CMake argument to set the CMake variable OPENOCD.

# Run west config once to set permanent CMake argument
west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe

# Do a pristine build once after setting CMake argument
west build -b cy8cproto_062_4343w -p always samples/basic/blinky

west flash
west debug

Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging on the PSOC 6 CM4 core.

Errata

Problem

Solution

The GPIO_INT_TRIG_BOTH interrupt is not raised when the associated GPIO is asserted.

This will be fixed in a future release.

GDB experiences a timeout error connecting to a server instance started by west debugserver.

This will be fixed in a future release.