T2G Body High Lite Evaluation Kit

Overview

The KIT_T2G-B-H_LITE is an evaluation kit based on the TRAVEO™ T2G Body High family, featuring a CYT4BF8CDS microcontroller with dual Arm® Cortex®-M7 cores and an Arm® Cortex®-M0+ core in a 176-pin TEQFP package. It is designed for automotive body electronics and industrial control applications.

Key features include 8 MB flash, 1 MB SRAM, CAN FD, Ethernet, dual 512-Mb QSPI NOR flash, and a comprehensive set of programmable analog and digital peripherals.

The board supports Arduino, Shield2Go, and MikroBUS headers and includes an onboard KitProg3 programmer/debugger with micro-B USB connectivity.

The KIT_T2G-B-H_LITE is a multi-core board with three build targets:

kit_t2g_b_h_lite/cyt4bf8cds/m0p — Cortex-M0+
kit_t2g_b_h_lite/cyt4bf8cds/m7_0 — Cortex-M7 core 0
kit_t2g_b_h_lite/cyt4bf8cds/m7_1 — Cortex-M7 core 1

Hardware

SoC: TRAVEO T2G Body High (CYT4BF8CDS)
CPU: Arm® Cortex®-M7 (×2) at 350 MHz + Arm® Cortex®-M0+ at 100 MHz
Package: 176-pin TEQFP
Flash: 8 MB
SRAM: 1 MB
Connectivity: CAN FD, Ethernet with RJ45
Peripherals: 2× 512-Mb QSPI NOR flash
Debug: Onboard KitProg3 (SWD + USB-UART + USB-I2C)
Power: Selectable 3.3V or 5.0V
Connector: Micro-B USB for programming and power
Expansion: Arduino, Shield2Go, MikroBUS headers
User I/O: Three user LEDs, two user buttons, potentiometer

For more information about the TRAVEO T2G Body High and KIT_T2G-B-H_LITE:

Kit Contents

TRAVEO T2G Body High Lite Evaluation Kit board
USB Type-A to Micro-B cable
Quick start guide

Supported Features

The kit_t2g_b_h_lite board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`kit_t2g_b_h_lite/cyt4bf8cds/m0p` target

On-target memory for this board target: 16 KiB of RAM, 512 KiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M0+ CPU1	`arm,cortex-m0+`
ARM architecture	on-chip	Infineon Serial Communication Blocks (SCB) node9	`infineon,scb`
Clock control	on-chip	Generic fixed-rate clock provider7	`fixed-clock`
Clock control	on-chip	Generic fixed factor clock provider12 6	`fixed-factor-clock`
Counter	on-chip	Infineon counters118	`infineon,counter`
DMA	on-chip	Infineon CAT1 DMA2	`infineon,dma`
Flash controller	on-chip	Infineon CAT1 flash controller1	`infineon,flash-controller`
GPIO & Headers	on-chip	Infineon GPIO Port2 22	`infineon,gpio`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	ARMv6-M NVIC (Nested Vectored Interrupt Controller) controller1	`arm,v6m-nvic`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
MTD	on-chip	Flash node5	`soc-nv-flash`
Pin control	on-chip	Infineon CAT1 Pinctrl Container1	`infineon,pinctrl`
SDHC	on-chip	Infineon CAT1 SDHC/SDIO controller1	`infineon,sdhc-sdio`
Serial controller	on-chip	Infineon CAT1 UART1	`infineon,uart`
SRAM	on-chip	Generic on-chip SRAM4	`mmio-sram`
Timer	on-chip	Infineon low power timer3	`infineon,lp-timer`
Timer	on-chip	ARMv6-M System Tick1	`arm,armv6m-systick`
Watchdog	on-chip	Infineon CAT1 Watchdog1	`infineon,watchdog`

`kit_t2g_b_h_lite/cyt4bf8cds/m7_0` target

On-target memory for this board target: 816 KiB of RAM, 2 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M7 CPU1	`arm,cortex-m7`
ARM architecture	on-chip	Infineon Serial Communication Blocks (SCB) node9	`infineon,scb`
Clock control	on-chip	Generic fixed-rate clock provider7	`fixed-clock`
Clock control	on-chip	Generic fixed factor clock provider12 6	`fixed-factor-clock`
Counter	on-chip	Infineon counters118	`infineon,counter`
DMA	on-chip	Infineon CAT1 DMA2	`infineon,dma`
Flash controller	on-chip	Infineon CAT1 flash controller1	`infineon,flash-controller`
GPIO & Headers	on-chip	Infineon GPIO Port2 22	`infineon,gpio`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	ARMv7-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v7m-nvic`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
MTD	on-chip	Flash node5	`soc-nv-flash`
Pin control	on-chip	Infineon CAT1 Pinctrl Container1	`infineon,pinctrl`
SDHC	on-chip	Infineon CAT1 SDHC/SDIO controller1	`infineon,sdhc-sdio`
Serial controller	on-chip	Infineon CAT1 UART1	`infineon,uart`
SRAM	on-chip	Generic on-chip SRAM4	`mmio-sram`
Timer	on-chip	Infineon low power timer3	`infineon,lp-timer`
Timer	on-chip	ARMv7-M System Tick1	`arm,armv7m-systick`
Watchdog	on-chip	Infineon CAT1 Watchdog1	`infineon,watchdog`

`kit_t2g_b_h_lite/cyt4bf8cds/m7_1` target

On-target memory for this board target: 64 KiB of RAM, 5824 KiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M7 CPU1	`arm,cortex-m7`
ARM architecture	on-chip	Infineon Serial Communication Blocks (SCB) node9	`infineon,scb`
Clock control	on-chip	Generic fixed-rate clock provider7	`fixed-clock`
Clock control	on-chip	Generic fixed factor clock provider12 6	`fixed-factor-clock`
Counter	on-chip	Infineon counters118	`infineon,counter`
DMA	on-chip	Infineon CAT1 DMA2	`infineon,dma`
Flash controller	on-chip	Infineon CAT1 flash controller1	`infineon,flash-controller`
GPIO & Headers	on-chip	Infineon GPIO Port2 22	`infineon,gpio`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	ARMv7-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v7m-nvic`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
MTD	on-chip	Flash node5	`soc-nv-flash`
Pin control	on-chip	Infineon CAT1 Pinctrl Container1	`infineon,pinctrl`
SDHC	on-chip	Infineon CAT1 SDHC/SDIO controller1	`infineon,sdhc-sdio`
Serial controller	on-chip	Infineon CAT1 UART1	`infineon,uart`
SRAM	on-chip	Generic on-chip SRAM4	`mmio-sram`
Timer	on-chip	Infineon low power timer3	`infineon,lp-timer`
Timer	on-chip	ARMv7-M System Tick1	`arm,armv7m-systick`
Watchdog	on-chip	Infineon CAT1 Watchdog1	`infineon,watchdog`

Connections and IOs

LEDs

Name	GPIO Pin
LED0	P5.0 (active low)
LED1	P5.1 (active low)
LED2	P5.2 (active low)

Push Buttons

Name	GPIO Pin
SW1	P5.3 (active low, pullup)
SW2	P17.0 (active low, pullup)

Default Zephyr Peripheral Mapping

Pin	Function	Usage
P0.1	SCB0 UART TX	Console TX
P0.0	SCB0 UART RX	Console RX
P0.2	SCB0 UART RTS	Console RTS
P0.3	SCB0 UART CTS	Console CTS
P5.0	GPIO	LED0
P5.1	GPIO	LED1
P5.2	GPIO	LED2
P5.3	GPIO	Button SW1
P17.0	GPIO	Button SW2

System Clock

The TRAVEO T2G Body High uses an External Crystal Oscillator (ECO) as the clock source. The clock path is:

FLL: ECO → 100 MHz
PLL: ECO → 80 MHz
CLK_HF0: 200 MHz (system clock)
CLK_HF1: 350 MHz (high-performance peripherals)

Serial Port

The TRAVEO T2G Body High has multiple SCB (Serial Communication Block) interfaces. The Zephyr console output is assigned to SCB0 (uart0), which is routed through the KitProg3 USB-UART bridge.

Default communication settings are 115200 8N1.

Building

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b kit_t2g_b_h_lite/cyt4bf8cds/m0p samples/hello_world

The same for the first Cortex®-M7 core:

# From the root of the zephyr repository
west build -b kit_t2g_b_h_lite/cyt4bf8cds/m7_0 samples/hello_world

And the second Cortex®-M7 core:

# From the root of the zephyr repository
west build -b kit_t2g_b_h_lite/cyt4bf8cds/m7_1 samples/hello_world

Note

Only the Cortex®-M0+ core is enabled at startup. To enable the first Cortex®-M7 core, add the following to the Cortex®-M0+ application: Cy_SysEnableCM7(CORE_CM7_0, CY_CORTEX_M7_0_APPL_ADDR);. To enable the second Cortex®-M7 core: Cy_SysEnableCM7(CORE_CM7_1, CY_CORTEX_M7_1_APPL_ADDR);.

Programming and Debugging

The kit_t2g_b_h_lite board supports the runners and associated west commands listed below.

	flash	debug	rtt	debugserver	attach
openocd	✅ (default)	✅ (default)	✅	✅	✅

The KIT_T2G-B-H_LITE includes an onboard programmer/debugger (KitProg3) which can be used to program and debug the TRAVEO T2G Body High cores.

Infineon OpenOCD Installation

The ModusToolbox™ Programming Tools package includes Infineon OpenOCD. Alternatively, a standalone installation can be done by downloading the Infineon OpenOCD release for your system and extracting the files to a location of your choice.

Note

Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox™ Programming Tools installation. When doing a standalone OpenOCD installation, this can be done manually by executing the script openocd/udev_rules/install_rules.sh.

Configuring a Console

Connect a USB cable from your PC to the KitProg3 micro-B USB connector (J2) on the KIT_T2G-B-H_LITE.Use the serial terminal of your choice (minicom, PuTTY, etc.) with the following settings:

Speed: 115200
Data: 8 bits
Parity: None
Stop bits: 1

Flashing

One time, set the Infineon OpenOCD path:

west config build.cmake-args -- "-DOPENOCD=path/to/infineon/openocd/bin/openocd.exe"

Build and flash the application:

west build -b kit_t2g_b_h_lite/cyt4bf8cds/m0p -p always samples/hello_world
west flash

One time, set the Infineon OpenOCD path:

west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd

Build and flash the application:

west build -b kit_t2g_b_h_lite/cyt4bf8cds/m0p -p always samples/hello_world
west flash

You should see the following message on the console:

*** Booting Zephyr OS build vX.Y.Z ***
Hello World! kit_t2g_b_h_lite

Debugging

# From the root of the zephyr repository
west build -b kit_t2g_b_h_lite/cyt4bf8cds/m0p samples/hello_world
west debug

Once the GDB console starts, you may set breakpoints and perform standard GDB debugging on the TRAVEO T2G Body High cores.