PSOC™ Edge E84 AI Evaluation Kit

Overview

The KIT_PSE84_AI is an evaluation kit based on the PSOC™ Edge E84 family, featuring a PSE846GPS2DBZC4A microcontroller with an Arm® Cortex®-M55 core at 400 MHz, an Arm® Cortex®-M33 core at 200 MHz, and an Arm® Ethos™-U55 NPU. It is designed for machine learning, wearables, and IoT applications.

Key features include 512-Mb QSPI NOR flash, 128-Mb Octal HYPERRAM™, AIROC™ CYW55513-based Wi-Fi + Bluetooth® connectivity (LBEE5HY2FY module), a rich sensor suite (6-axis IMU, magnetometer, barometric pressure, humidity, radar), MIPI-DSI display interface, analog and digital microphones, and an OV7675 DVP camera module.

The board includes an onboard KitProg3 programmer/debugger with USB Type-C connectivity, expansion IO header, and Raspberry Pi compatible MIPI-DSI display support.

Board Targets

The KIT_PSE84_AI provides the following build targets:

Build Target	Description
`kit_pse84_ai/pse846gps2dbzc4a/m33`	CM33 Secure — primary target for flashing and debugging
`kit_pse84_ai/pse846gps2dbzc4a/m33/ns`	CM33 Non-Secure — TF-M variant
`kit_pse84_ai/pse846gps2dbzc4a/m55`	CM55 — requires `--sysbuild` flag

Note

CM55 builds must use the --sysbuild flag. Sysbuild automatically creates the CM33 enable_cm55 companion application required to boot the CM55 core.

Note

The CM33 secure image is automatically signed with imgtool during the build process. The build outputs a .signed.hex file suitable for flashing. The non-secure (TF-M) variant outputs a tfm_merged.hex file.

Hardware

SoC: PSOC™ Edge E84 (PSE846GPS2DBZC4A)
Primary CPU: Arm® Cortex®-M55 at 400 MHz
Secondary CPU: Arm® Cortex®-M33 at 200 MHz
NPU: Arm® Ethos™-U55
Flash: 512-Mb QSPI NOR flash
RAM: 128-Mb Octal HYPERRAM
Wireless: LBEE5HY2FY module — Wi-Fi + Bluetooth® (AIROC CYW55513)
Sensors: 6-axis IMU, 3-axis magnetometer, barometric pressure, humidity, radar
Display: MIPI-DSI (Raspberry Pi compatible)
Audio: Analog and digital microphones
USB: Type-C (device)
Expansion: Expansion IO header
User I/O: User LEDs and user button
Security: Arm® TrustZone®-M, secure enclave with crypto accelerators
Debug: Onboard KitProg3 (SWD + UART bridge)
Power: Active HP / Deep Sleep idle, VDDA/VDDD: 1800 mV

For more information about the PSOC™ Edge E84 and KIT_PSE84_AI:

Kit Contents

PSOC™ Edge E84 AI Evaluation Kit board
OV7675 DVP camera module

Supported Features

The kit_pse84_ai board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`kit_pse84_ai/pse846gps2dbzc4a/m33` target

On-target memory for this board target: 132 KiB of RAM, 64 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33 CPU1	`arm,cortex-m33`
ADC	on-chip	PSOC Edge AutAnalog SAR ADC1	`infineon,autanalog-sar-adc`
ARM architecture	on-chip	Infineon Serial Communication Blocks (SCB) node10	`infineon,scb`
Audio	on-chip	Infineon PDM (Pulse Density Modulation) Controller1	`infineon,pdm`
CAN	on-chip	Infineon CAN FD controller wrapper. 1	`infineon,canfd-controller`
CAN	on-chip	Infineon MCAN Driver2	`infineon,can`
Clock control	on-chip	Generic fixed-rate clock provider5	`infineon,fixed-clock`
	on-chip	Generic fixed-rate clock provider20	`infineon,fixed-factor-clock`
	on-chip	infineon peripheral divider2 24	`infineon,peri-div`
Comparator	on-chip	Infineon Low Power Comparator (LPComp) for CAT1 family1	`infineon,lp-comp`
Comparator	on-chip	Infineon LPComp channel node (child of infineon,lp-comp)2	`infineon,lp-comp-channel`
Counter	on-chip	Infineon TCPWM counter32	`infineon,tcpwm-counter`
DAC	on-chip	PSOC Edge AutAnalog CT DAC2	`infineon,autanalog-ctdac`
DMA	on-chip	Infineon CAT1 DMA2	`infineon,dma`
Flash controller	on-board	Infineon CAT1 QSPI flash controller1	`infineon,qspi-flash`
GPIO & Headers	on-chip	Infineon GPIO Port11 11	`infineon,gpio`
I2C	on-chip	Infineon CAT1 I2C driver1	`infineon,i2c`
I2S	on-chip	Infineon I2S Controller2	`infineon,i2s`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v8m-nvic`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
Multi-Function Device	on-chip	Infineon AutAnalog (Autonomous Analog) Multi-Function Device1	`infineon,autanalog`
	on-chip	Infineon AutAnalog Continuous Time Block (CTB) MFD2	`infineon,autanalog-ctb`
	on-chip	Infineon AutAnalog Programmable Threshold Comparator (PTComp) MFD1	`infineon,autanalog-ptcomp`
	on-chip	Infineon AutAnalog Programmable Reference Block (PRB) MFD1	`infineon,autanalog-prb`
MTD	on-chip	Flash node4	`soc-nv-flash`
Pin control	on-chip	Infineon CAT1 Pinctrl Container1	`infineon,pinctrl`
PWM	on-chip	Infineon TCPWM PWM32	`infineon,tcpwm-pwm`
RTC	on-chip	Infineon CAT1 family RTC device1	`infineon,rtc`
SDHC	on-chip	Infineon CAT1 SDHC/SDIO controller2	`infineon,sdhc-sdio`
Sensors	on-board	The BMI270 is an inertial measurement unit1	`bosch,bmi270`
	on-board	Infineon DPS310 temperature and pressure sensor1	`infineon,dps310`
	on-board	Sensirion SHT4x humidity and temperature sensor1	`sensirion,sht4x`
Serial controller	on-chip	Infineon CAT1 UART1	`infineon,uart`
SRAM	on-chip	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	Infineon low power timer1 1	`infineon,lp-timer`
	on-chip	Infineon TCPWM Timer32	`infineon,tcpwm`
	on-chip	ARMv8-M System Tick1	`arm,armv8m-systick`
USB	on-chip	Infineon USBHS1	`infineon,usbhs`
Watchdog	on-chip	Infineon CAT1 Watchdog1	`infineon,watchdog`

`kit_pse84_ai/pse846gps2dbzc4a/m33/ns` target

On-target memory for this board target: 256 KiB of RAM, 64 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33 CPU1	`arm,cortex-m33`
ADC	on-chip	PSOC Edge AutAnalog SAR ADC1	`infineon,autanalog-sar-adc`
ARM architecture	on-chip	Infineon PSE84 frontend of Arm Ethos-U NPU1	`infineon,edge-npu`
ARM architecture	on-chip	Infineon Serial Communication Blocks (SCB) node10	`infineon,scb`
Audio	on-chip	Infineon PDM (Pulse Density Modulation) Controller1	`infineon,pdm`
CAN	on-chip	Infineon CAN FD controller wrapper. 1	`infineon,canfd-controller`
CAN	on-chip	Infineon MCAN Driver2	`infineon,can`
Clock control	on-chip	Generic fixed-rate clock provider5	`infineon,fixed-clock`
	on-chip	Generic fixed-rate clock provider20	`infineon,fixed-factor-clock`
	on-chip	infineon peripheral divider2 24	`infineon,peri-div`
Comparator	on-chip	Infineon Low Power Comparator (LPComp) for CAT1 family1	`infineon,lp-comp`
Comparator	on-chip	Infineon LPComp channel node (child of infineon,lp-comp)2	`infineon,lp-comp-channel`
Counter	on-chip	Infineon TCPWM counter32	`infineon,tcpwm-counter`
DAC	on-chip	PSOC Edge AutAnalog CT DAC2	`infineon,autanalog-ctdac`
DMA	on-chip	Infineon CAT1 DMA2	`infineon,dma`
Flash controller	on-board	Infineon CAT1 QSPI flash controller1	`infineon,qspi-flash`
GPIO & Headers	on-chip	Infineon GPIO Port11 11	`infineon,gpio`
I2C	on-chip	Infineon CAT1 I2C driver1	`infineon,i2c`
I2S	on-chip	Infineon I2S Controller2	`infineon,i2s`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v8m-nvic`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
Multi-Function Device	on-chip	Infineon AutAnalog (Autonomous Analog) Multi-Function Device1	`infineon,autanalog`
	on-chip	Infineon AutAnalog Continuous Time Block (CTB) MFD2	`infineon,autanalog-ctb`
	on-chip	Infineon AutAnalog Programmable Threshold Comparator (PTComp) MFD1	`infineon,autanalog-ptcomp`
	on-chip	Infineon AutAnalog Programmable Reference Block (PRB) MFD1	`infineon,autanalog-prb`
MTD	on-chip	Flash node4	`soc-nv-flash`
Pin control	on-chip	Infineon CAT1 Pinctrl Container1	`infineon,pinctrl`
PWM	on-chip	Infineon TCPWM PWM32	`infineon,tcpwm-pwm`
RTC	on-chip	Infineon CAT1 family RTC device1	`infineon,rtc`
SDHC	on-chip	Infineon CAT1 SDHC/SDIO controller2	`infineon,sdhc-sdio`
Sensors	on-board	The BMI270 is an inertial measurement unit1	`bosch,bmi270`
	on-board	Infineon DPS310 temperature and pressure sensor1	`infineon,dps310`
	on-board	Sensirion SHT4x humidity and temperature sensor1	`sensirion,sht4x`
Serial controller	on-chip	Infineon CAT1 UART1	`infineon,uart`
SRAM	on-chip	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	Infineon low power timer1 1	`infineon,lp-timer`
	on-chip	Infineon TCPWM Timer32	`infineon,tcpwm`
	on-chip	ARMv8-M System Tick1	`arm,armv8m-systick`
USB	on-chip	Infineon USBHS1	`infineon,usbhs`
Watchdog	on-chip	Infineon CAT1 Watchdog1	`infineon,watchdog`

`kit_pse84_ai/pse846gps2dbzc4a/m55` target

On-target memory for this board target: 256 KiB of RAM, 64 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M55 CPU1	`arm,cortex-m55`
ADC	on-chip	PSOC Edge AutAnalog SAR ADC1	`infineon,autanalog-sar-adc`
ARM architecture	on-chip	Infineon PSE84 frontend of Arm Ethos-U NPU1	`infineon,edge-npu`
ARM architecture	on-chip	Infineon Serial Communication Blocks (SCB) node9	`infineon,scb`
Audio	on-chip	Infineon PDM (Pulse Density Modulation) Controller1	`infineon,pdm`
Bluetooth	on-board	Connectivity chip that uses Infineon Bluetooth Host Controller Interface UART driver1	`infineon,bt-hci-uart`
CAN	on-chip	Infineon CAN FD controller wrapper. 1	`infineon,canfd-controller`
CAN	on-chip	Infineon MCAN Driver2	`infineon,can`
Clock control	on-chip	Generic fixed-rate clock provider2 3	`infineon,fixed-clock`
	on-chip	Generic fixed-rate clock provider20	`infineon,fixed-factor-clock`
	on-chip	infineon peripheral divider4 22	`infineon,peri-div`
Comparator	on-chip	Infineon Low Power Comparator (LPComp) for CAT1 family1	`infineon,lp-comp`
Comparator	on-chip	Infineon LPComp channel node (child of infineon,lp-comp)2	`infineon,lp-comp-channel`
Counter	on-chip	Infineon TCPWM counter32	`infineon,tcpwm-counter`
DAC	on-chip	PSOC Edge AutAnalog CT DAC2	`infineon,autanalog-ctdac`
DMA	on-chip	Infineon CAT1 DMA2	`infineon,dma`
Flash controller	on-board	Infineon CAT1 QSPI flash controller1	`infineon,qspi-flash`
GPIO & Headers	on-chip	Infineon GPIO Port13 9	`infineon,gpio`
I2C	on-chip	Infineon CAT1 I2C driver1	`infineon,i2c`
I2S	on-chip	Infineon I2S Controller2	`infineon,i2s`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v8.1m-nvic`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
Multi-Function Device	on-chip	Infineon AutAnalog (Autonomous Analog) Multi-Function Device1	`infineon,autanalog`
	on-chip	Infineon AutAnalog Continuous Time Block (CTB) MFD2	`infineon,autanalog-ctb`
	on-chip	Infineon AutAnalog Programmable Threshold Comparator (PTComp) MFD1	`infineon,autanalog-ptcomp`
	on-chip	Infineon AutAnalog Programmable Reference Block (PRB) MFD1	`infineon,autanalog-prb`
MTD	on-chip	Flash node4	`soc-nv-flash`
Pin control	on-chip	Infineon CAT1 Pinctrl Container1	`infineon,pinctrl`
PWM	on-chip	Infineon TCPWM PWM32	`infineon,tcpwm-pwm`
RTC	on-chip	Infineon CAT1 family RTC device1	`infineon,rtc`
SDHC	on-chip	Infineon CAT1 SDHC/SDIO controller1 1	`infineon,sdhc-sdio`
Sensors	on-board	The BMI270 is an inertial measurement unit1	`bosch,bmi270`
	on-board	Infineon DPS310 temperature and pressure sensor1	`infineon,dps310`
	on-board	Sensirion SHT4x humidity and temperature sensor1	`sensirion,sht4x`
Serial controller	on-chip	Infineon CAT1 UART2	`infineon,uart`
SRAM	on-chip	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	Infineon low power timer1 1	`infineon,lp-timer`
	on-chip	Infineon TCPWM Timer32	`infineon,tcpwm`
	on-chip	ARMv8.1-M System Tick1	`arm,armv8.1m-systick`
USB	on-chip	Infineon USBHS1	`infineon,usbhs`
Watchdog	on-chip	Infineon CAT1 Watchdog1	`infineon,watchdog`
Wi-Fi	on-board	AIROC Wi-Fi Connectivity1	`infineon,airoc-wifi`

Connections and IOs

LEDs

Name	GPIO Pin
LED0	P10.7 (active HIGH)
LED1	P10.5 (active HIGH)
LED_RED	P20.6 (active HIGH)
LED_GREEN	P20.4 (active HIGH)
LED_BLUE	P20.5 (active HIGH)

Push Buttons

Name	GPIO Pin
SW0	P7.0 (active low, pull-up)

Default Zephyr Peripheral Mapping

Pin	Function	Usage
P6.7	SCB2 UART TX	Console TX
P6.5	SCB2 UART RX	Console RX
P10.1	SCB4 UART TX	BT HCI TX
P10.0	SCB4 UART RX	BT HCI RX
P10.3	SCB4 UART RTS	BT HCI RTS
P10.2	SCB4 UART CTS	BT HCI CTS
P10.7	GPIO	LED0
P10.5	GPIO	LED1
P20.6	GPIO	LED_RED
P20.4	GPIO	LED_GREEN
P20.5	GPIO	LED_BLUE
P7.0	GPIO	Button SW0

System Clock

The PSOC™ Edge E84 uses 14 high-frequency clocks. The primary clock configuration is:

CLK_HF0: 200 MHz (system clock)
CLK_HF1: 400 MHz (CM55 core)
CLK_HF2: 300 MHz
CLK_HF4: 400 MHz

Serial Port

The PSOC™ Edge E84 console output is assigned to SCB2 (uart2), which is routed through the KitProg3 USB-UART bridge.

Default communication settings are 115200 8N1.

The BT HCI UART is assigned to SCB4 (uart4) with hardware flow control (RTS/CTS).

Building

Here is an example for the Hello World application on the CM33 core.

# From the root of the zephyr repository
west build -b kit_pse84_ai/pse846gps2dbzc4a/m33 samples/hello_world

To build the CM33 non-secure (TF-M) variant:

west build -p -b kit_pse84_ai/pse846gps2dbzc4a/m33/ns samples/hello_world

To build for the CM55 core, use the --sysbuild flag:

west build -p -b kit_pse84_ai/pse846gps2dbzc4a/m55 samples/hello_world --sysbuild

Note

The --sysbuild flag is required for CM55 builds. Sysbuild automatically creates the CM33 enable_cm55 companion application that boots the CM55 core.

Programming and Debugging

The kit_pse84_ai board supports the runners and associated west commands listed below.

	flash	debug	debugserver	attach	rtt
openocd	✅ (default)	✅ (default)	✅	✅	✅
probe-rs	✅	✅	✅	✅

The KIT_PSE84_AI includes an onboard programmer/debugger (KitProg3) which can be used to program and debug the PSOC™ Edge E84 cores.

Infineon OpenOCD Installation

The ModusToolbox™ Programming Tools package includes Infineon OpenOCD. Alternatively, a standalone installation can be done by downloading the Infineon OpenOCD release for your system and extracting the files to a location of your choice.

Note

Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox™ Programming Tools installation. When doing a standalone OpenOCD installation, this can be done manually by executing the script openocd/udev_rules/install_rules.sh.

Configuring a Console

Connect a USB cable from your PC to the KitProg3 USB Type-C connector (J1) on the KIT_PSE84_AI.Use the serial terminal of your choice (minicom, PuTTY, etc.) with the following settings:

Speed: 115200
Data: 8 bits
Parity: None
Stop bits: 1

Flashing

One time, set the Infineon OpenOCD path:

west config build.cmake-args -- "-DOPENOCD=path/to/infineon/openocd/bin/openocd.exe"

Build and flash the application (CM33):

west build -b kit_pse84_ai/pse846gps2dbzc4a/m33 -p always samples/hello_world
west flash

Build and flash the application (CM33 non-secure / TF-M):

west build -b kit_pse84_ai/pse846gps2dbzc4a/m33/ns -p always samples/hello_world
west flash

Build and flash the application (CM55 with sysbuild):

west build -b kit_pse84_ai/pse846gps2dbzc4a/m55 -p always samples/hello_world --sysbuild
west flash

One time, set the Infineon OpenOCD path:

west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd

Build and flash the application (CM33):

west build -b kit_pse84_ai/pse846gps2dbzc4a/m33 -p always samples/hello_world
west flash

Build and flash the application (CM33 non-secure / TF-M):

west build -b kit_pse84_ai/pse846gps2dbzc4a/m33/ns -p always samples/hello_world
west flash

Build and flash the application (CM55 with sysbuild):

west build -b kit_pse84_ai/pse846gps2dbzc4a/m55 -p always samples/hello_world --sysbuild
west flash

You should see the following message on the console:

*** Booting Zephyr OS build vX.Y.Z ***
Hello World! kit_pse84_ai

Debugging

# From the root of the zephyr repository
west build -b kit_pse84_ai/pse846gps2dbzc4a/m33 samples/hello_world
west debug

Once the GDB console starts, you may set breakpoints and perform standard GDB debugging on the PSOC™ Edge E84 CM33 core.

Secure Boot

The PSOC™ Edge E84 MCU includes an extended boot stage in ROM that, on reset, jumps to the first application image. On the KIT-PSE84-AI the destination is selected by the level of the boot pin, which by default is pulled HIGH and causes the ROM extended boot to jump to the first application located in external flash.

To make the ROM extended boot jump to a first application located in internal RRAM, one of the following must be done:

Hardware rework: remove resistor R188 and populate resistor R187 to pull the boot pin LOW.
Reprovisioning (no hardware rework): reprovision the device using the same flow described in Enabling Secure Boot below, but customize the generated OEM policy JSON to ignore the boot pin state. While following the provisioning steps, after the OEM key pair has been generated, set oem_alt_boot to false in policy/policy_oem_provisioning.json in the project, before provisioning the kit.

In either case, the boot behavior is then locked to booting from RRAM and must be reverted (reattaching R188 / removing R187, or reprovisioning again with oem_alt_boot set back to true) to re-enable booting from external flash.

In all cases the first application image must be in MCUboot image format, i.e. it must be preceded by an MCUboot image header (magic number, header size, vector table address, image size) and followed by the trailer with the hash/signature TLVs. Out of the box, the device is not provisioned for secure boot, so the ROM extended boot only checks the image format and hash; no cryptographic signature verification is performed against a provisioned key.

The MCUboot image format is produced automatically by the soc/infineon/edge/pse84/pse84_metadata.cmake helper pse84_add_metadata_secure_hex(), which invokes imgtool sign with the header address, header size and slot size derived from the devicetree memory map. By default this helper does not pass a signing key, which is sufficient for a non-provisioned device.

Enabling Secure Boot

To enable real signature verification by the ROM extended boot, the device must be reprovisioned. Follow sections 2.2.1, 2.2.2 and 2.2.3 of the PSOC™ Edge Security Getting Started Application Note to:

Generate (or import) the OEM signing key pair.
Provision the device with the corresponding public key and lifecycle transition.
Program the desired security counter / anti-rollback value.

After the device has been reprovisioned, the pse84_add_metadata_secure_hex() function in soc/infineon/edge/pse84/pse84_metadata.cmake must be updated so that imgtool sign also receives the signing key and a security counter. The relevant additions are:

${PYTHON_EXECUTABLE} ${IMGTOOL} sign --version "0.0.0+0"
  --header-size ${header_size} --erased-val 0xff --pad-header
  --slot-size ${slot_size} --hex-addr ${header_addr}
  --key <oem-private-key-file>
  --security-counter <value>
  ${INPUT_FILE} ${OUTPUT_FILE}

Where <oem-private-key-file> is the path to the OEM private key file (e.g. a .pem file) matching the public key provisioned into the device, and <value> is the security counter assigned during provisioning. Without these additional parameters, images built for a provisioned device will be rejected by the ROM extended boot.

TF-M Multicore Support

The PSOC™ Edge E84 supports a TF-M paired-build configuration where the CM33 Non-Secure application acts as the PSA client local to the secure firmware, and the CM55 Non-Secure application reaches the same TF-M Secure Processing Environment running on the CM33 through a mailbox-based relay. This is enabled with the Kconfig option CONFIG_PSOC_EDGE_M55_SRF_SUPPORT, which must be set on both images.

Note

The CM55 image in this configuration is not built using sysbuild. Both images are built as standalone Zephyr applications, and they must be flashed independently. The paired build is coordinated through a CMake variable rather than through sysbuild.

Build Order and Dependency

The CM55 build consumes the PSA manifest headers generated by the CM33-NS TF-M build, so the CM33-NS image must be built first. The CM55 CMake configuration expects the CM33-NS build output to be available at configure time and will fail with a FATAL_ERROR if it cannot find the directory <cm33-ns-build>/tfm/generated/interface/include.

By default the CM55 build looks for the CM33-NS build output at ${ZEPHYR_BASE}/build. When a different output directory is used (e.g. via west build -d), its path must be passed to the CM55 build through the PSE84_CM33_BUILD_DIR CMake variable.

Building

Build the CM33-NS image with mailbox/relay support enabled:

west build -b kit_pse84_ai/pse846gps2dbzc4a/m33/ns samples/hello_world -- -DCONFIG_PSOC_EDGE_M55_SRF_SUPPORT=y

The example below uses an explicit build directory:

west build -b kit_pse84_ai/pse846gps2dbzc4a/m33/ns \
           -d build_multicore_33 samples/hello_world \
           -- -DCONFIG_PSOC_EDGE_M55_SRF_SUPPORT=y

Build the CM55-NS image, pointing it at the CM33-NS build directory from the previous step via PSE84_CM33_BUILD_DIR:

west build -b kit_pse84_ai/pse846gps2dbzc4a/m55 \
           -d build_multicore_55 samples/basic/blinky \
           -- -DCONFIG_PSOC_EDGE_M55_SRF_SUPPORT=y \
              -DPSE84_CM33_BUILD_DIR=build_multicore_33

If the CM33-NS image was built with the default build directory, the -DPSE84_CM33_BUILD_DIR=... argument may be omitted.

Flashing

The two images are independent flash artifacts and must be programmed separately. Flash the CM55 image first as the CM33-NS image will try to boot the CM55 image on reset and will fault if it cannot find a valid image to jump to.

west flash -d build_multicore_55
west flash -d build_multicore_33

PSOC™ Edge E84 AI Evaluation Kit

Overview

Board Targets

Hardware

Kit Contents

Supported Features

kit_pse84_ai/pse846gps2dbzc4a/m33 target

kit_pse84_ai/pse846gps2dbzc4a/m33/ns target

kit_pse84_ai/pse846gps2dbzc4a/m55 target

Connections and IOs

LEDs

Push Buttons

Default Zephyr Peripheral Mapping

System Clock

Serial Port

Building

Programming and Debugging

Infineon OpenOCD Installation

Configuring a Console

Flashing

Debugging

Secure Boot

Enabling Secure Boot

TF-M Multicore Support

Build Order and Dependency

Building

Flashing

References

`kit_pse84_ai/pse846gps2dbzc4a/m33` target

`kit_pse84_ai/pse846gps2dbzc4a/m33/ns` target

`kit_pse84_ai/pse846gps2dbzc4a/m55` target