PolarFire SoC Icicle Kit

Overview

The Microchip PolarFire SoC Icicle Kit is a PolarFire SoC FPGA based development board with a Microchip MPFS250T FPGA device. The E51 RISC-V CPU can be deployed on the mpfs_icicle board. More information can be found on the Microchip website.

Hardware

Supported Features

The mpfs_icicle board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`mpfs_icicle/polarfire/e51` target

Type	Location	Description	Compatible
CPU	on-chip	SiFive E51 Standard Core CPU1	`sifive,e51`
CPU	on-chip	SiFive U54 Standard Core CPU4	`sifive,u54`
GPIO & Headers	on-chip	Microchip PolarFire SoC GPIO1 2	`microchip,mpfs-gpio`
I2C	on-chip	Microchip MPFS I2C Controller2	`microchip,mpfs-i2c`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	RISC-V CPU interrupt controller5	`riscv,cpu-intc`
	on-chip	SiFive RISC-V Core-Local Interruptor1	`sifive,clint0`
	on-chip	SiFive RISCV-V platform-local interrupt controller1	`sifive,plic-1.0.0`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
MTD	on-board	Properties supporting Zephyr spi-nor flash driver (over the Zephyr SPI API) control of serial flash memories using the standard M25P80-based command set2	`jedec,spi-nor`
Reset controller	on-chip	Microchip MPFS Reset Controller (SOFT_RESET_CR, SUBBLK_CLOCK_CR)1	`microchip,mpfs-reset`
Serial controller	on-chip	ns16550 UART1 4	`ns16550`
SPI	on-chip	Microchip Polarfire SOC QSPI controller2	`microchip,mpfs-qspi`
SPI	on-chip	Microchip Polarfire SOC SPI controller1	`microchip,mpfs-spi`
SRAM	on-chip	Generic on-chip SRAM2	`mmio-sram`
System controller	on-chip	System Controller Registers R/W1	`syscon`
Timer	on-chip	RISC-V Machine Timer1	`riscv,machine-timer`

`mpfs_icicle/polarfire/u54` target

Type	Location	Description	Compatible
CPU	on-chip	SiFive E51 Standard Core CPU1	`sifive,e51`
CPU	on-chip	SiFive U54 Standard Core CPU4	`sifive,u54`
GPIO & Headers	on-chip	Microchip PolarFire SoC GPIO1 2	`microchip,mpfs-gpio`
I2C	on-chip	Microchip MPFS I2C Controller2	`microchip,mpfs-i2c`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	RISC-V CPU interrupt controller5	`riscv,cpu-intc`
	on-chip	SiFive RISC-V Core-Local Interruptor1	`sifive,clint0`
	on-chip	SiFive RISCV-V platform-local interrupt controller1	`sifive,plic-1.0.0`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
MTD	on-board	Properties supporting Zephyr spi-nor flash driver (over the Zephyr SPI API) control of serial flash memories using the standard M25P80-based command set2	`jedec,spi-nor`
Reset controller	on-chip	Microchip MPFS Reset Controller (SOFT_RESET_CR, SUBBLK_CLOCK_CR)1	`microchip,mpfs-reset`
Serial controller	on-chip	ns16550 UART2 3	`ns16550`
SPI	on-chip	Microchip Polarfire SOC QSPI controller2	`microchip,mpfs-qspi`
SPI	on-chip	Microchip Polarfire SOC SPI controller1	`microchip,mpfs-spi`
SRAM	on-chip	Generic on-chip SRAM2	`mmio-sram`
System controller	on-chip	System Controller Registers R/W1	`syscon`
Timer	on-chip	RISC-V Machine Timer1	`riscv,machine-timer`

`mpfs_icicle/polarfire/u54/smp` target

Type	Location	Description	Compatible
CPU	on-chip	SiFive E51 Standard Core CPU1	`sifive,e51`
CPU	on-chip	SiFive U54 Standard Core CPU4	`sifive,u54`
GPIO & Headers	on-chip	Microchip PolarFire SoC GPIO1 2	`microchip,mpfs-gpio`
I2C	on-chip	Microchip MPFS I2C Controller2	`microchip,mpfs-i2c`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	RISC-V CPU interrupt controller5	`riscv,cpu-intc`
	on-chip	SiFive RISC-V Core-Local Interruptor1	`sifive,clint0`
	on-chip	SiFive RISCV-V platform-local interrupt controller1	`sifive,plic-1.0.0`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
MTD	on-board	Properties supporting Zephyr spi-nor flash driver (over the Zephyr SPI API) control of serial flash memories using the standard M25P80-based command set2	`jedec,spi-nor`
Reset controller	on-chip	Microchip MPFS Reset Controller (SOFT_RESET_CR, SUBBLK_CLOCK_CR)1	`microchip,mpfs-reset`
Serial controller	on-chip	ns16550 UART2 3	`ns16550`
SPI	on-chip	Microchip Polarfire SOC QSPI controller2	`microchip,mpfs-qspi`
SPI	on-chip	Microchip Polarfire SOC SPI controller1	`microchip,mpfs-spi`
SRAM	on-chip	Generic on-chip SRAM2	`mmio-sram`
System controller	on-chip	System Controller Registers R/W1	`syscon`
Timer	on-chip	RISC-V Machine Timer1	`riscv,machine-timer`

Programming and debugging

Building

Applications for the mpfs_icicle board configuration can be built as usual (see Building an Application):

west build -b mpfs_icicle

To build the default SMP capable variant

west build -b mpfs_icicle/polarfire/smp

Flashing

In order to upload the application to the device, you’ll need OpenOCD and GDB with RISC-V support. You can get them as a part of SoftConsole SDK. Download and installation instructions can be found on Microchip’s SoftConsole website.

With the necessary tools installed, you can connect to the board using OpenOCD. To establish an OpenOCD connection run:

sudo LD_LIBRARY_PATH=<softconsole_path>/openocd/bin \
<softconsole_path>/openocd/bin/openocd --command "set DEVICE MPFS" --file \
<softconsole_path>/openocd/share/openocd/scripts/board/microsemi-riscv.cfg

Leave it running, and in a different terminal, use GDB to upload the binary to the board. You can use the RISC-V GDB from a toolchain delivered with SoftConsole SDK.

Here is the GDB terminal command to connect to the device and load the binary:

<softconsole_path>/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-gdb \
-ex "target extended-remote localhost:3333" \
-ex "set mem inaccessible-by-default off" \
-ex "set arch riscv:rv64" \
-ex "set riscv use_compressed_breakpoints no" \
-ex "load" <path_to_executable>

Debugging

Refer to the detailed overview of Application Debugging.