ESP32-P4-Function-EV-Board

Overview

ESP32-P4-Function-EV-Board is an evaluation board from Espressif built around the ESP32-P4 SoC, a high-performance dual-core RISC-V MCU running up to 400 MHz. The board pairs the bare SoC with 16 MB of on-board flash and 8 MB of external PSRAM, and exposes USB Serial/JTAG, MIPI CSI/DSI, SD card and expansion headers for application development. For more information, check ESP32-P4-Function-EV-Board [6].

Hardware

ESP32-P4-Function-EV-Board ships with:

  • ESP32-P4 SoC paired with 16 MB on-board flash and 8 MB external PSRAM

  • USB-C connector wired to the on-chip USB Serial/JTAG controller

  • MIPI CSI camera connector

  • MIPI DSI display connector

  • microSD card slot

  • Boot and reset buttons

  • Expansion headers exposing UART, I2C, SPI and GPIO

ESP32-P4 Features

ESP32-P4 is Espressif’s high-performance MCU featuring a dual-core 32-bit RISC-V high-performance (HP) processor running up to 400 MHz, plus a low-power (LP) 32-bit RISC-V coprocessor. It targets human-machine interface (HMI) and edge-computing applications with an integrated L2 cache, high-bandwidth memory interfaces, and rich connectivity options.

ESP32-P4 includes the following features:

  • Dual core 32-bit RISC-V HP processor with a clock speed of up to 400 MHz

  • 32-bit RISC-V LP processor with a clock speed of up to 40 MHz

  • 768 KB of high-performance SRAM

  • 32 KB of low-power SRAM

  • 128 KB of ROM

  • L1 instruction and data caches plus a unified L2 cache

  • Up to 64 MB of external PSRAM in HEX or octal mode

  • Up to 16 MB of external flash

Digital interfaces:

  • 55 programmable GPIOs

  • 5x UART

  • 1x Low-power (LP) UART

  • 2x General purpose SPI

  • 2x I2C

  • 1x Low-power (LP) I2C

  • 3x I2S

  • 1x SDIO 3.0 host controller with 2 slots

  • 1x USB 2.0 OTG High-Speed (HS) with embedded PHY

  • 1x USB Serial/JTAG controller

  • 1x 10/100 Mbit Ethernet MAC with RMII interface

  • 1x MIPI-CSI camera interface

  • 1x MIPI-DSI display interface

  • 1x JPEG codec

  • 1x 2D Pixel Processing Accelerator (PPA)

  • LED PWM controller, up to 8 channels

  • 2x Motor control PWM (MCPWM)

  • 3x TWAI controller, compatible with ISO 11898-1 (CAN Specification 2.0)

  • 1x Pulse counter

  • 1x Remote control peripheral

  • General DMA controller (GDMA) over AHB and AXI buses

  • Event task matrix (ETM)

Analog interfaces:

  • 1x 12-bit SAR ADC

  • 1x temperature sensor

Timers:

  • 1x 52-bit system timer

  • 2x 54-bit general-purpose timers

  • 2x Watchdog timers

Low Power:

  • Multiple power modes designed for typical scenarios: Active, Modem-sleep, Light-sleep, Deep-sleep

  • 4-channel programmable on-chip LDO regulators

  • Power Management Unit (PMU) with dedicated retention DMA

Security:

  • Secure boot

  • Flash encryption

  • Cryptographic hardware acceleration: AES-128/256, SHA, RSA, ECC, HMAC, Digital signature, ECDSA

  • True random number generator (TRNG)

  • Key manager

Low-Power CPU (LP CORE)

The ESP32-P4 SoC has a Low-Power (LP) 32-bit RISC-V coprocessor in addition to the dual HP cores. The LP Core features ultra low power consumption, an interrupt controller, a debug module and a system bus interface for memory and peripheral access.

The LP Core is in sleep mode by default. It has two application scenarios:

  • Power insensitive scenario: When the HP cores are active, the LP Core can assist with some speed and efficiency-insensitive controls and computations.

  • Power sensitive scenario: When the HP cores are in the power-down state to save power, the LP Core can be woken up to handle some external wake-up events.

The LP Core support is fully integrated with Sysbuild (System build). The user can enable the LP Core by adding the following configuration to the project:

CONFIG_ESP32_ULP_COPROC_ENABLED=y

See Low-Power CPU (LP CORE) folder as code reference.

For more information, check the ESP32-P4 Datasheet [1] or the ESP32-P4 Technical Reference Manual [2].

Supported Features

The esp32p4_function_ev_board board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

esp32p4_function_ev_board/esp32p4/hpcore target

On-target memory for this board target: 768 KiB of RAM, 16 MiB of Flash.

Type

Location

Description

Compatible

CPU

on-chip

Espressif RISC-V CPU2

espressif,riscv

ADC

on-chip

ESP32 ADC1

espressif,esp32-adc

CAN

on-chip

ESP32 Two-Wire Automotive Interface (TWAI)3

espressif,esp32-twai

Clock control

on-chip

ESP32 Clock (Power & Clock Controller Module) Module1

espressif,esp32-clock

Counter

on-chip

ESP32 general-purpose timers2

espressif,esp32-timer

on-chip

ESP32 counters2

espressif,esp32-counter

Cryptographic accelerator

on-chip

Espressif ESP32 SHA Hardware Accelerator1

espressif,esp32-sha

on-chip

Espressif ESP32 family AES Hardware Accelerator1

espressif,esp32-aes

DMA

on-chip

ESP32 GDMA (General Direct Memory Access)2

espressif,esp32-gdma

Ethernet

on-chip

ESP32 Ethernet1

espressif,esp32-eth

on-chip

ESP32 MDIO controller1

espressif,esp32-mdio

Flash controller

on-chip

ESP32 flash controller1

espressif,esp32-flash-controller

GPIO & Headers

on-chip

ESP32 GPIO controller2

espressif,esp32-gpio

I2C

on-chip

ESP32 I2C12

espressif,esp32-i2c

I2S

on-chip

ESP32 I2S3

espressif,esp32-i2s

Input

on-board

Group of GPIO-bound input keys1

gpio-keys

Interrupt controller

on-chip

ESP32 Interrupt controller1

espressif,esp32-intc

Mailbox

on-chip

ESP32 soft mailbox1

espressif,mbox-esp32

Memory controller

on-chip

ESP32 pseudo-static RAM controller1

espressif,esp32-psram

MTD

on-chip

Flash node1

soc-nv-flash

Pin control

on-chip

ESP32 pin controller1

espressif,esp32-pinctrl

PWM

on-chip

ESP32 LED Control (LEDC)1

espressif,esp32-ledc

on-chip

ESP32 Motor Control Pulse Width Modulator (MCPWM)2

espressif,esp32-mcpwm

Regulator

on-chip

Espressif ESP32 on-chip LDO voltage regulators1

espressif,esp32-regulator

RNG

on-chip

ESP32 TRNG (True Random Number Generator)1

espressif,esp32-trng

SDHC

on-chip

ESP32 SDHC controller1

espressif,esp32-sdhc

on-chip

ESP32 SDHC controller slot11

espressif,esp32-sdhc-slot

Sensors

on-chip

ESP32 internal temperature sensor1

espressif,esp32-temp

on-chip

ESP32 Pulse Counter (PCNT)1

espressif,esp32-pcnt

Serial controller

on-chip

ESP32 UART15

espressif,esp32-uart

on-chip

ESP32 UART1

espressif,esp32-usb-serial

SPI

on-chip

ESP32 SPI controller11

espressif,esp32-spi

Timer

on-chip

ESP32 System Timer1

espressif,esp32-systimer

USB

on-chip

DesignWare OTG USB 2.0 controller1

snps,dwc2

Watchdog

on-chip

ESP32 watchdog11

espressif,esp32-watchdog

esp32p4_function_ev_board/esp32p4/lpcore target

On-target memory for this board target: 32 KiB of RAM, 16 MiB of Flash.

Type

Location

Description

Compatible

CPU

on-chip

Espressif RISC-V CPU1

espressif,riscv

Flash controller

on-chip

ESP32 flash controller1

espressif,esp32-flash-controller

GPIO & Headers

on-chip

ESP32 GPIO controller1

espressif,esp32-gpio

Interrupt controller

on-chip

ESP32 Interrupt controller1

espressif,esp32-intc

Mailbox

on-chip

ESP32 soft mailbox1

espressif,mbox-esp32

MTD

on-chip

Flash node1

soc-nv-flash

Serial controller

on-chip

ESP32 Low Power UART1

espressif,esp32-lpuart

SRAM

on-chip

Generic on-chip SRAM1

mmio-sram

System Requirements

Binary Blobs

Espressif HAL requires RF binary blobs in order work. Run the command below to retrieve those files.

west blobs fetch hal_espressif

Note

It is recommended running the command above after west update.

Programming and Debugging

The esp32p4_function_ev_board board supports the runners and associated west commands listed below.

flash debug debugserver rtt attach
esp32 ✅ (default)
openocd ✅ ✅ (default) ✅ ✅ ✅

Simple Boot

The board could be loaded using the single binary image, without 2nd stage bootloader. It is the default option when building the application without additional configuration.

Note

Simple boot does not provide any security features nor OTA updates.

MCUboot Bootloader

User may choose to use MCUboot bootloader instead. In that case the bootloader must be built (and flashed) at least once.

There are two options to be used when building an application:

  1. Sysbuild

  2. Manual build

Note

User can select the MCUboot bootloader by adding the following line to the board default configuration file.

CONFIG_BOOTLOADER_MCUBOOT=y

Sysbuild

The sysbuild makes possible to build and flash all necessary images needed to bootstrap the board with the ESP32 SoC.

To build the sample application using sysbuild use the command:

west build -b <board> --sysbuild samples/hello_world

By default, the ESP32 sysbuild creates bootloader (MCUboot) and application images. But it can be configured to create other kind of images.

Build directory structure created by sysbuild is different from traditional Zephyr build. Output is structured by the domain subdirectories:

build/
├── hello_world
│   └── zephyr
│       ├── zephyr.elf
│       └── zephyr.bin
├── mcuboot
│    └── zephyr
│       ├── zephyr.elf
│       └── zephyr.bin
└── domains.yaml

Note

With --sysbuild option the bootloader will be re-build and re-flash every time the pristine build is used.

For more information about the system build please read the Sysbuild (System build) documentation.

Manual Build

During the development cycle, it is intended to build & flash as quickly possible. For that reason, images can be built one at a time using traditional build.

The instructions following are relevant for both manual build and sysbuild. The only difference is the structure of the build directory.

Note

Remember that bootloader (MCUboot) needs to be flash at least once.

Build and flash applications as usual (see Building an Application and Run an Application for more details).

# From the root of the zephyr repository
west build -b <board> samples/hello_world

The usual flash target will work with the board configuration. Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b <board> samples/hello_world
west flash

Note

On targets that expose the built-in USB Serial/JTAG controller, the chip can stay in download mode after west flash and will not boot the new image until it is power cycled. If that happens, flash with a watchdog reset so the chip restarts on its own:

west flash --reset-type watchdog-reset

Faster Flashing

To speed up the development cycle, --esp-skip-flashed skips writing the image when the binary already in flash matches the one being flashed, verified with an MD5 check on the device:

west flash --esp-skip-flashed

For an even faster reflash, --esp-diff writes only the regions that differ from the previously flashed image. It compares against a locally cached copy rather than reading the device, so use it only when the flash was not modified by another tool, board, or manual write since the last west flash:

west flash --esp-diff

Progress output can be suppressed for cleaner logs, which is useful in CI:

west flash --esp-no-progress

Open the serial monitor using the following command:

west espressif monitor

After the board has automatically reset and booted, you should see the following message in the monitor:

***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
Hello World! <board>

Debugging

OpenOCD Debugging

Espressif chips require a custom OpenOCD build with ESP32-specific patches. Download the latest release from OpenOCD for ESP32 [3].

For detailed JTAG setup instructions, see JTAG debugging for ESP32 [5].

Zephyr Thread Awareness

OpenOCD supports Zephyr RTOS thread awareness, allowing GDB to:

  • List all threads with info threads

  • Display thread names, priorities, and states

  • Switch between thread contexts

  • Show backtraces for any thread

Requirements:

Example:

# From the root of the zephyr repository
west build -b <board> samples/hello_world -- -DCONFIG_DEBUG_THREAD_INFO=y -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
west debug

Using a Custom OpenOCD

The Zephyr SDK includes a bundled OpenOCD, but it may not have ESP32 support. To use the Espressif OpenOCD, specify the path when building:

# From the root of the zephyr repository
west build -b <board> samples/hello_world -- -DOPENOCD=/path/to/openocd -DOPENOCD_DEFAULT_PATH=/path/to/openocd/scripts
west debug

References