FRDM-MCXA166

Overview

FRDM-MCXA166 are compact and scalable development boards for rapid prototyping of MCX A16X MCUs. They offer industry standard headers for easy access to the MCUs I/Os, integrated open-standard serial interfaces and an on-board MCU-Link debugger. MCX A Series are high-performance, low-power microcontrollers with MAU,SmartDMA and performance efficiency.

Hardware

  • MCX-A166 Arm Cortex-M33 microcontroller running at 180 MHz

  • 1MB dual-bank on chip Flash

  • 256 KB RAM

  • 1x FlexCAN with FD, 1x RGB LED, 3x SW buttons

  • On-board MCU-Link debugger with CMSIS-DAP

  • Arduino Header, SmartDMA/Camera Header, mikroBUS

For more information about the MCX-A166 SoC and FRDM-MCXA166 board, see:

Supported Features

The frdm_mcxa166 board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
frdm_mcxa166
/
mcxa166

Type

Location

Description

Compatible

CPU

on-chip

ARM Cortex-M33F CPU1

arm,cortex-m33f

Clock control

on-chip

LPC SYSCON & CLKCTL IP node1

nxp,lpc-syscon

Flash controller

on-chip

NXP MSF1 Flash Memory Module (FMU)1

nxp,msf1

GPIO & Headers

on-chip

Kinetis GPIO5

nxp,kinetis-gpio

Input

on-board

Group of GPIO-bound input keys1

gpio-keys

Interrupt controller

on-chip

ARMv8-M NVIC (Nested Vectored Interrupt Controller)1

arm,v8m-nvic

LED

on-board

Group of GPIO-controlled LEDs1

gpio-leds

MTD

on-chip

Flash node1

soc-nv-flash

Pin control

on-chip

NXP PORT Pin Controller5

nxp,port-pinmux

on-chip

NXP PORT Pin Controller1

nxp,port-pinctrl

Reset controller

on-chip

LPC SYSCON Peripheral reset controller1

nxp,lpc-syscon-reset

Serial controller

on-chip

NXP LPUART1

nxp,lpuart

SRAM

on-chip

Generic on-chip SRAM2

mmio-sram

Timer

on-chip

ARMv8-M System Tick1

arm,armv8m-systick

Connections and IOs

The MCX-A166 SoC has 6 gpio controllers and has pinmux registers which can be used to configure the functionality of a pin.

Name

Function

Usage

PIO2_3

UART

UART RX

PIO2_2

UART

UART TX

System Clock

The MCX-A166 SoC is configured to use FRO running at 180MHz as a source for the system clock.

Serial Port

The FRDM-MCXA166 SoC has 6 LPUART interfaces for serial communication. LPUART 2 is configured as UART for the console.

Programming and Debugging

Build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

A debug probe is used for both flashing and debugging the board. This board is configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.

Using LinkServer

Linkserver is the default runner for this board, and supports the factory default MCU-Link firmware. Follow the instructions in MCU-Link CMSIS-DAP Onboard Debug Probe to reprogram the default MCU-Link firmware. This only needs to be done if the default onboard debug circuit firmware was changed. To put the board in ISP mode to program the firmware, short jumper JP4.

Configuring a Console

Connect a USB cable from your PC to J15, and use the serial terminal of your choice (minicom, putty, etc.) with the following settings:

  • Speed: 115200

  • Data: 8 bits

  • Parity: None

  • Stop bits: 1

Flashing

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b frdm_mcxa166 samples/hello_world
west flash

Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:

*** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
Hello World! frdm_mcxa166/mcxa166

Debugging

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b frdm_mcxa166/mcxa166 samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

*** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
Hello World! frdm_mcxa166/mcxa166

Troubleshooting

Using Segger SystemView and RTT

Note that when using SEGGER SystemView or RTT with this SOC, the RTT control block address must be set manually within SystemView or the RTT Viewer. The address provided to the tool should be the location of the _SEGGER_RTT symbol, which can be found using a debugger or by examining the zephyr.map file output by the linker.

The RTT control block address must be provided manually because this SOC supports ECC RAM. If the SEGGER tooling searches the ECC RAM space for the control block a fault will occur, provided that ECC is enabled and the RAM segment being searched has not been initialized to a known value.

Support Resources for Zephyr