RM1261 DVK
Overview
The RM1261 Development Kit provides support for the Ezurio RM1261 LoRa module.
The module includes an EFR32BG22 Arm Cortex-M33 CPU and a Semtech SX1261 LoRa radio.
The RM1261 module incorporates the QFN package EFR32BG22 (512kB Flash, 32kB RAM). The part features up to 16 configurable GPIOs and Lora Radio TX Power up to 15dBm.
The kit features a USB interface, an on-board SEGGER J-Link debugger, one user-LED and button, and support for hardware add-on boards via a mikroBUS socket and a Qwiic connector.
Note
You can find more information about the RM126x family of modules in the RM126x product brief, the RM126x datasheet and on the RM126x website.
You can find more information about the underlying EFR32BG22 SoC in the EFR32BG22 datasheet and EFR32BG22 reference manual.
You can find more information about the Semtech SX1261 LoRa radio in the SX126x datasheet.
Hardware
The RM1261 DVK has one crystal oscillator as follows.
Low-frequency 32.768 kHz crystal oscillator (LFXO)
The crystal oscillator is fitted within the RM1261 module.
The module supports an external LoRa antenna.
Note
The MHF4 connector exposed via the RM1261 shield can should be used for antenna connectivity.
Full details of the DVK can be found in the RM126x DVK user guide and RM1261 DVK schematics.
Supported Features
The rm126x_dvk_rm1261 board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
rm126x_dvk_rm1261/efr32bg22c224f512im40 target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M33 CPU1 |
|
ADC |
on-chip |
Silicon Labs Series 2 IADC1 |
|
Bluetooth |
on-chip |
Silicon Labs Series 2 Bluetooth HCI1 |
|
Clock control |
on-chip |
Silicon Labs Series 2 CMU1 |
|
on-chip |
Silicon Labs Series 2 HFXO1 |
||
on-chip |
Silicon Labs Series 2 HFRCODPLL1 |
||
on-chip |
Generic fixed-rate clock provider3 |
||
on-chip |
Silicon Labs Series 2 LFXO1 |
||
on-chip |
Silicon Labs Series 2 LFRCO1 |
||
on-chip |
Generic fixed factor clock provider18 |
||
Debug |
on-chip |
Silicon Labs Packet Trace Interface1 |
|
on-chip |
ARMv8 instrumentation trace macrocell1 |
||
DMA |
on-chip |
Silicon Labs Series 2 LDMA1 |
|
Flash controller |
on-chip |
Silicon Labs Series 2 MSC1 |
|
GPIO & Headers |
on-chip |
Silicon Labs Series 2 GPIO Peripheral1 |
|
on-chip |
Silicon Labs Series 2 GPIO Port4 |
||
on-board |
GPIO pins exposed on Mikro BUS headers1 |
||
on-board |
STEMMA QT is a 4-pin JST-SH connector for I2C devices1 |
||
I2C |
on-chip |
Silabs I2C node2 |
|
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv8-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
on-board |
Group of PWM-controlled LEDs1 |
||
LoRa |
on-board |
Semtech SX1261 LoRa Modem1 |
|
MMU / MPU |
on-chip |
ARMv8-M MPU (Memory Protection Unit)1 |
|
MTD |
on-chip |
Flash node1 |
|
on-board |
Fixed partitions of a flash (or other non-volatile storage) memory1 |
||
Networking |
on-chip |
Silicon Labs Series 2 Radio Interface1 |
|
Pin control |
on-chip |
Silicon Labs Series 2 DBUS Pin Controller1 |
|
PWM |
on-chip |
||
on-chip |
Silicon Labs LETIMER PWM1 |
||
Regulator |
on-chip |
Silicon Labs Series 2 DC-DC converter1 |
|
Retained memory |
on-chip |
Silicon Labs Series 2 BURAM1 |
|
RNG |
on-chip |
GECKO TRNG (True Random Number Generator)1 |
|
RTC |
on-chip |
Silicon Labs Series 2 RTCC1 |
|
Serial controller |
on-chip |
Silicon Labs Series 2 EUSART 1 |
|
SPI |
on-chip |
Silicon Labs Series 2 USART2 |
|
SRAM |
on-chip |
Generic on-chip SRAM1 |
|
Timer |
on-chip |
ARMv8-M System Tick1 |
|
on-chip |
|||
on-chip |
Silicon Labs Series 2 BURTC1 |
||
on-chip |
Silicon Labs LETIMER1 |
||
Watchdog |
on-chip |
Silicon Labs Series 1-2 WDOG1 |
DVK Connections and IOs
In the following table, the column Name contains Pin names. For example, PA2 means Pin number 2 on PORTA, as used in the board’s datasheets and manuals.
The Direction column indicates the pin direction from the module perspective, with I indicating Input, O Output and I/O both.
Name |
Function |
Usage |
Direction |
|---|---|---|---|
PA1 |
SWD_SWCLK |
JLink SWCLK |
I |
PA2 |
SWD_SWDIO |
JLink SWDIO |
I/O |
PA3 |
SWD_SWO |
JLink SWO |
O |
PB2 |
EUART0_RTS |
UART Console VCOM_RTS |
O |
PB3 |
EUART0_RX |
UART Console VCOM_RX |
I |
PB4 |
EUART0_CTS |
UART Console VCOM_CTS |
I |
PC0 |
USART0_SCK |
mikroBUS SCK |
O |
PC1 |
GPIO |
mikroBUS CS |
I/O |
PC2 |
GPIO |
mikroBUS AN |
I |
PC3 |
GPIO |
mikroBUS RST |
O |
PC4 |
GPIO |
mikroBUS PWM |
O |
PC5 |
GPIO |
mikroBUS INT / LED0 |
I/O |
PC6 |
GPIO |
Button 0 |
I |
PC7 |
EUART0_TX |
UART Console VCOM_TX |
O |
PD2 |
USART0_RX / I2C0_SCL |
mikroBUS MISO / mikroBUS RX / mikroBUS SCL / Qwiic SCL |
I/O |
PD3 |
USART0_TX / I2C0_SDA |
mikroBUS MOSI / mikroBUS TX / mikroBUS SDA / Qwiic SDA |
I/O |
Note
MikroBUS INT and LED0 are multiplexed to the same I/O. Usage is determined by solder bridge SB4. Refer to the RM126x DVK user guide and RM1261 DVK schematics for further details.
The solder bridge defaults to the closed position to enable LED0 connectivity.
Note
MikroBUS MISO, RX and SCL are multiplexed to the same I/O. Usage is determined by solder bridges SB5, SB7 and SB8. Refer to the RM126x DVK user guide and RM1261 DVK schematics for further details.
The SB7 solder bridge defaults to closed to enable MISO connectivity.
Note
MikroBUS MOSI, TX and SDA are multiplexed to the same I/O. Usage is determined by solder bridges SB9, SB11 and SB12. Refer to the RM126x DVK user guide and RM1261 DVK schematics for further details.
The SB11 solder bridge defaults to closed to enable MOSI connectivity.
Note
Qwiic SCL is multipexed to the same I/O as MikroBUS MISO, RX and SCL. MikroBUS I2C based boards can be used in conjunction with Qwiic based boards by closing solder bridges SB5 and SB6.
Qwiic SDA is multipexed to the same I/O as MikroBUS MOSI, TX and SDA. MikroBUS I2C based boards can be used in conjunction with Qwiic based boards by closing solder bridges SB9 and SB10.
Refer to the RM126x DVK user guide and RM1261 DVK schematics for further details.
EFR32BG22 To SX1261 Radio Connections
The following are internal to the RM1261 module and describe connectivity between the EFR32BG22 SoC and the SX1261 LoRa radio.
In the following table, the column Name contains Pin names. For example, PA2 means Pin number 2 on PORTA, as used in the board’s datasheets and manuals.
The Direction column indicates the pin direction from the SoC perspective, with I indicating Input and O Output.
Name |
Function |
Usage |
Direction |
|---|---|---|---|
PA0 |
USART1_SCK |
SX1261 SCK |
O |
PA4 |
USART1_TX |
SX1261 MOSI |
O |
PA5 |
GPIO |
SX1261 DIO1 |
I |
PA6 |
GPIO |
SX1261 RESET |
O |
PA7 |
GPIO |
SX1261 BUSY |
I |
PA8 |
USART1_RX |
SX1261 MISO |
I |
PB0 |
GPIO |
SX1261 CS |
O |
PB1 |
GPIO |
SX1261 ANT SW |
O |
SX1261 Radio Connections
In the following table, the column Name contains Pin names as defined in the SX126x datasheet.
The Direction column indicates the pin direction from the radio perspective, with O indicating Output.
Name |
Function |
Usage |
Direction |
|---|---|---|---|
DIO2 |
GPIO |
RF Direction |
O |
DIO3 |
GPIO |
TCXO Enable |
O |
System Clock
The RM1261 is configured to use the internal HFRCO oscillator as the System Clock at 38MHz. It can operate at clock speeds of up to 80 MHz.
Serial Port
The RM1261 has two USARTs and one EUART.
USART0 is mapped to the mikroBUS SPI port.
USART1 is dedicated to the SX1261 radio.
EUART0 is connected to the board controller and is used for the console.
Programming and Debugging
Applications for the rm126x_dvk_rm1261 board can be built, flashed, and debugged in the usual way.
See Building an Application and Run an Application for more details on building and running.
Note
Before using the kit, you should update the J-Link firmware in Simplicity Studio.
Testing LoRa
The LoRaWAN class A device sample can be programmed to an RM1261 DVK to demonstrate joining and uplinking to a LoRaWAN network server.
This is built as follows.
# From the root of the zephyr repository
west build -b rm126x_dvk_rm1261 samples/subsys/lorawan/class_a