Kit T2G-C2-D-6M Lite
Overview
The KIT_T2G-C-2D-6M_LITE kit enables you to evaluate and develop applications using the TRAVEO™ T2G Cluster 2D family CYT4DN device. The TRAVEO™ T2G CYT4DN MCU is specifically designed for automotive instrument cluster and Head-Up Display (HUD) applications and it is a true programmable embedded system-on-chip, integrating two 320-MHz Arm® Cortex®-M7 CPUs as the primary application processors, a 100-MHz Arm® Cortex®-M0+ that supports the following:
Low-power operations (Active, Sleep, Low-power Sleep, Deep Sleep, and Hibernate modes)
6336 KB code-flash with additional 128 KB work-flash and 640 KB SRAM
Programmable analog and digital peripherals that allow faster time-to-market
Hardware
For more information about KIT_T2G-C-2D-6M_LITE:
Kit Features
Evaluation board for CYT4DN MCU in 327-BGA package, dual-core Arm® Cortex® M7 CPUs running at 320-MHz and an Arm® Cortex® M0+ CPU running at 100-MHz
Full-system approach on the board, featuring Gigabit Ethernet PHY and connector, CAN FD transceiver, user LEDs, buttons, and potentiometer
Headers compatible with Arduino for interfacing Arduino shields
Fully compatible with ModusToolbox™ v3.0
KitProg3 on-board SWD programmer/debugger, USB-UART, and USB-I2C bridge functionality through USB connector
Evaluation board supports operating voltages from 3.3 V to 5.0 V for CYT4DN
Supported Features
The kit_t2g_c2d6m_lite board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
kit_t2g_c2d6m_lite/cyt4dnjbzs/m0p target
On-target memory for this board target: 30 KiB of RAM, 6336 KiB of Flash.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M0+ CPU1 |
|
on-chip |
ARM Cortex-M7 CPU2 |
||
ARM architecture |
on-chip |
Infineon Serial Communication Blocks (SCB) node10 |
|
Clock control |
on-chip |
Infineon Clock Oscillators1 |
|
on-chip |
|||
on-chip |
|||
on-chip |
Generic fixed factor clock provider2 |
||
on-chip |
Infineon peripheral clock group2 |
||
on-chip |
|||
GPIO & Headers |
on-chip |
||
Interrupt controller |
on-chip |
ARMv6-M NVIC (Nested Vectored Interrupt Controller) controller1 |
|
on-chip |
Infineon CAT1 CPUSS system interrupt multiplexer1 |
||
on-chip |
Infineon CAT1 CPUSS interrupt multiplexer channel8 |
||
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
MTD |
on-chip |
Flash node1 |
|
Pin control |
on-chip |
Infineon CAT1 Pinctrl Container1 |
|
Serial controller |
on-chip |
||
SRAM |
on-chip |
Generic on-chip SRAM3 |
|
Timer |
on-chip |
ARMv6-M System Tick1 |
kit_t2g_c2d6m_lite/cyt4dnjbzs/m7_0 target
On-target memory for this board target: 224 KiB of RAM, 6336 KiB of Flash.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M0+ CPU1 |
|
on-chip |
|||
ARM architecture |
on-chip |
Infineon Serial Communication Blocks (SCB) node10 |
|
Clock control |
on-chip |
Infineon Clock Oscillators1 |
|
on-chip |
|||
on-chip |
|||
on-chip |
Generic fixed factor clock provider2 |
||
on-chip |
Infineon peripheral clock group2 |
||
on-chip |
|||
GPIO & Headers |
on-chip |
||
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv7-M NVIC (Nested Vectored Interrupt Controller)1 |
|
on-chip |
Infineon CAT1 CPUSS system interrupt multiplexer1 |
||
on-chip |
Infineon CAT1 CPUSS interrupt multiplexer channel8 |
||
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
MTD |
on-chip |
Flash node1 |
|
Pin control |
on-chip |
Infineon CAT1 Pinctrl Container1 |
|
Serial controller |
on-chip |
||
SRAM |
on-chip |
Generic on-chip SRAM3 |
|
Timer |
on-chip |
ARMv7-M System Tick1 |
kit_t2g_c2d6m_lite/cyt4dnjbzs/m7_1 target
On-target memory for this board target: 256 KiB of RAM, 6336 KiB of Flash.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M0+ CPU1 |
|
on-chip |
|||
ARM architecture |
on-chip |
Infineon Serial Communication Blocks (SCB) node9 |
|
Clock control |
on-chip |
Infineon Clock Oscillators1 |
|
on-chip |
|||
on-chip |
|||
on-chip |
Generic fixed factor clock provider2 |
||
on-chip |
Infineon peripheral clock group2 |
||
on-chip |
|||
GPIO & Headers |
on-chip |
||
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv7-M NVIC (Nested Vectored Interrupt Controller)1 |
|
on-chip |
Infineon CAT1 CPUSS system interrupt multiplexer1 |
||
on-chip |
Infineon CAT1 CPUSS interrupt multiplexer channel8 |
||
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
MTD |
on-chip |
Flash node1 |
|
Pin control |
on-chip |
Infineon CAT1 Pinctrl Container1 |
|
Serial controller |
on-chip |
||
SRAM |
on-chip |
Generic on-chip SRAM3 |
|
Timer |
on-chip |
ARMv7-M System Tick1 |
Programming and Debugging
The kit_t2g_c2d6m_lite board supports the runners and associated west commands listed below.
| flash | debug | debugserver | rtt | attach | |
|---|---|---|---|---|---|
| openocd | ✅ (default) | ✅ (default) | ✅ | ✅ | ✅ |
Building
Build the Hello World sample application for the Cortex®-M0+ core:
# From the root of the zephyr repository
west build -b kit_t2g_c2d6m_lite/cyt4dnjbzs/m0p samples/hello_world
To release the Cortex®-M7 cores from M0+ during boot, pass the corresponding Kconfig option(s) at build time. Only enable a core when valid firmware is present at its flash address; otherwise the core will fetch invalid instructions and fault.
# From the root of the zephyr repository
west build -b kit_t2g_c2d6m_lite/cyt4dnjbzs/m0p samples/hello_world -- -DCONFIG_SOC_SERIES_CYT4DN_START_M7_0=y -DCONFIG_SOC_SERIES_CYT4DN_START_M7_1=y
Build for the Cortex®-M7 Core 0:
# From the root of the zephyr repository
west build -b kit_t2g_c2d6m_lite/cyt4dnjbzs/m7_0 samples/hello_world
Build for the Cortex®-M7 Core 1:
# From the root of the zephyr repository
west build -b kit_t2g_c2d6m_lite/cyt4dnjbzs/m7_1 samples/hello_world
Note
Per the CYT4DN start-up sequence, only the Cortex®-M0+ core is released from reset by ROM/flash boot. The Cortex®-M0+ application is responsible for enabling the Cortex®-M7 cores: it sets CLK_HF1 for CM7_0 and CM7_1, programs the vector table bases (CM7_0_VECTOR_TABLE_BASE at 0x40200200 and CM7_1_VECTOR_TABLE_BASE at 0x40200600), enables power for both M7 cores, clears CPU_WAIT, and releases the cores from reset.
Flashing
The KIT_T2G_C-2D-6M_LITE includes an onboard programmer/debugger (KitProg3 [6]) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed.
Both the full ModusToolbox [3] and the ModusToolbox Programming Tools [4] packages include Infineon OpenOCD. Installing either of these packages will also install Infineon OpenOCD. If neither package is installed, a minimal installation can be done by downloading the Infineon OpenOCD [5] release for your system and manually extract the files to a location of your choice.
Note
Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script openocd/udev_rules/install_rules.sh.
The path to the installed Infineon OpenOCD executable must be available to the west tool commands. The examples below use a permanent CMake argument to set the CMake variable OPENOCD.
Set the OpenOCD path once:
west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd
Build and flash for the Cortex®-M0+ core:
# From the root of the zephyr repository
west build -b kit_t2g_c2d6m_lite/cyt4dnjbzs/m0p -p always samples/hello_world
west flash
west debug
Build and flash for the Cortex®-M0+ core with M7 cores released during boot:
# From the root of the zephyr repository
west build -b kit_t2g_c2d6m_lite/cyt4dnjbzs/m0p -p always samples/hello_world -- -DCONFIG_SOC_SERIES_CYT4DN_START_M7_0=y -DCONFIG_SOC_SERIES_CYT4DN_START_M7_1=y
west flash
west debug
Build and flash for the Cortex®-M7 Core 0:
# From the root of the zephyr repository
west build -b kit_t2g_c2d6m_lite/cyt4dnjbzs/m7_0 -p always samples/hello_world
west flash
west debug
Build and flash for the Cortex®-M7 Core 1:
# From the root of the zephyr repository
west build -b kit_t2g_c2d6m_lite/cyt4dnjbzs/m7_1 -p always samples/hello_world
west flash
west debug
Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging.