PSOC™ Control C3M5 Connectivity Card 2

Overview

The KIT_PSC3M5_CC2 is the connectivity card supplied with the KIT_PSC3M5_MC1 motor control kit. It is based on the PSOC™ Control C3 family, featuring a PSOC™ Control C3M5 (PSC3M5FDS2AFQ1) microcontroller with an Arm® Cortex®-M33 core. The card carries the control and communication interfaces for the kit, while the companion power board carries the inverter stage.

Key features include 256 KB flash, 64 KB SRAM, an isolated CAN FD interface, advanced timers with high-resolution capability, and a high-performance programmable analog subsystem.

The board supports a mikroBUS expansion socket and includes an onboard isolated SEGGER J-Link LITE programmer/debugger.

Hardware

SoC: PSOC™ Control C3M5 (PSC3M5FDS2AFQ1, PG-E-LQFP-80)
CPU: Arm® Cortex®-M33, configured at 180 MHz
Flash: 256 KB
SRAM: 64 KB
Connectivity: Isolated CAN FD, SCB (UART/SPI/I2C)
Peripherals: TCPWM timers, programmable analog (HPPASS)
Security: Arm® TrustZone®-M
Debug: Onboard isolated SEGGER J-Link LITE (SWD + UART bridge)
Expansion: mikroBUS socket, 100-pin power board connector
User I/O: Two user LEDs, one user button, two potentiometers

For more information about the PSOC™ Control C3 and KIT_PSC3M5_CC2:

Supported Features

The kit_psc3m5_cc2 board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`kit_psc3m5_cc2/psc3m5fds2afq1` target

On-target memory for this board target: 64 KiB of RAM, 256 KiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33 CPU1	`arm,cortex-m33`
ADC	on-chip	PSOC C3 HPPASS SAR ADC1	`infineon,hppass-sar-adc`
ARM architecture	on-chip	Infineon Serial Communication Blocks (SCB) node4	`infineon,scb`
CAN	on-chip	Infineon CAN FD controller wrapper. 1	`infineon,canfd-controller`
CAN	on-chip	Infineon MCAN Driver1 1	`infineon,can`
Clock control	on-chip	Generic fixed-rate clock provider5 1	`infineon,fixed-clock`
	on-chip	Generic fixed-rate clock provider8 1	`infineon,fixed-factor-clock`
	on-chip	infineon peripheral divider3 21	`infineon,peri-div`
Comparator	on-chip	Infineon Low Power Comparator (LPComp) for CAT1 family1	`infineon,lp-comp`
	on-chip	Infineon LPComp channel node (child of infineon,lp-comp)2	`infineon,lp-comp-channel`
	on-chip	Infineon HPPASS CSG comparator5	`infineon,hppass-csg-comp`
Counter	on-chip	Infineon TCPWM counter20	`infineon,tcpwm-counter`
Cryptographic accelerator	on-chip	Infineon MXCRYPTOLITE True Random Number Generator1	`infineon,mxcryptolite-trng`
Cryptographic accelerator	on-chip	Infineon MXCRYPTOLITE crypto engine (AES / SHA-256)1	`infineon,mxcryptolite-crypto`
DAC	on-chip	Infineon HPPASS CSG DAC5	`infineon,hppass-csg-dac`
DMA	on-chip	Infineon CAT1 DMA2	`infineon,dma`
Flash controller	on-chip	Infineon CAT1 flash controller1	`infineon,flash-controller`
GPIO & Headers	on-chip	Infineon GPIO Port10	`infineon,gpio`
GPIO & Headers	on-board	GPIO pins exposed on Mikro BUS headers1	`mikro-bus`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v8m-nvic`
IPC	on-chip	Infineon inter-processor communication (IPC) instance1	`infineon,ipc`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
Multi-Function Device	on-chip	Infineon HPPASS (High Performance Programmable Analog Sub-System) Multi-Function Device1	`infineon,hppass-analog`
	on-chip	Infineon HPPASS Comparator Slope Generator (CSG) MFD.1	`infineon,hppass-csg`
	on-chip	Infineon MXCRYPTOLITE multi-function device1	`infineon,mxcryptolite`
MTD	on-chip	Flash node1	`soc-nv-flash`
Pin control	on-chip	Infineon CAT1 Pinctrl Container1	`infineon,pinctrl`
Power management	on-chip	Infineon hibernate / hibernate-RAM wakeup source configuration1	`infineon,hibernate-wakeup`
Power management	on-chip	Infineon CAT1B power control1	`infineon,cat1b-power`
PWM	on-chip	Infineon TCPWM PWM20	`infineon,tcpwm-pwm`
RTC	on-chip	Infineon CAT1 family RTC device1	`infineon,rtc`
Serial controller	on-chip	Infineon CAT1 UART1	`infineon,uart`
SPI	on-chip	Infineon CAT1 SPI1	`infineon,spi`
SRAM	on-chip	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	ARMv8-M System Tick1	`arm,armv8m-systick`
	on-chip	Infineon low power timer1	`infineon,lp-timer`
	on-chip	Infineon TCPWM Timer20	`infineon,tcpwm`
Watchdog	on-chip	Infineon CAT1 Watchdog1	`infineon,watchdog`

Connections and IOs

LEDs

Name	GPIO Pin
LED0	P9.4 (active low)
LED1	P9.5 (active low)

Neither user LED can be driven from hardware PWM – P9.4 and P9.5 have no TCPWM option.

Push Buttons

Name	GPIO Pin
SW1	P4.6 (active low)

Default Zephyr Peripheral Mapping

Pin	Function	Usage
P2.2	SCB1 UART RX	Console RX
P2.3	SCB1 UART TX	Console TX
P6.2	CAN1 RX	CAN FD receive
P6.3	CAN1 TX	CAN FD transmit
P5.0	SCB3 SPI MOSI	mikroBUS MOSI
P5.1	SCB3 SPI MISO	mikroBUS MISO
P5.2	SCB3 SPI CLK	mikroBUS SCK
P5.3	SCB3 SPI SELECT0	mikroBUS CS
P0.0	GPIO	mikroBUS INT
P0.1	GPIO	mikroBUS PWM
P9.4	GPIO	LED0
P9.5	GPIO	LED1
P4.6	GPIO	Button SW1

System Clock

The PSOC™ Control C3M5 runs from the internal oscillator. The configured clock path is:

FLL: 96 MHz
DPLL-LP0: 180 MHz
DPLL-LP1: 240 MHz
CLK_HF0: 180 MHz (system clock)
CLK_HF2: 80 MHz (peripheral group 4: UART, CAN FD, SPI)
CLK_HF3: 240 MHz

CLK_HF2 is divided to 80 MHz so that the CAN FD bit timing meets CiA 601-3.

A 16 MHz crystal is fitted on P1.0 and P1.1. Zephyr does not currently provide an external crystal oscillator clock node for PSOC™ Control C3, so it is unused. No 32.768 kHz watch crystal is fitted, so the watch crystal oscillator is disabled in the board devicetree and P0.0 and P0.1 are routed to the mikroBUS socket instead.

Serial Port

The PSOC™ Control C3M5 has six SCB (Serial Communication Block) interfaces that can be configured as UART, SPI, or I2C. The Zephyr console output is assigned to SCB1 (uart1), which is routed through the onboard J-Link LITE USB-UART bridge. Hardware flow control is not routed on this board.

Default communication settings are 115200 8N1.

CAN FD

The CAN interface is galvanically isolated. The controller signals reach an Infineon TLE9371VSJ transceiver through a 2DIB1400F dual digital isolator:

P6.3 CAN1_TX --> INA  ==||== OUTA --> TXD --+ TLE9371VSJ +-- CANH
P6.2 CAN1_RX <-- OUTB ==||== INB  <-- RXD --+  STB = GND +-- CANL
                  2DIB1400F

The transceiver standby pin is tied to the isolated ground. Standby is active high, so the transceiver is permanently in normal mode and requires no software control. The board devicetree therefore contains no can-transceiver-gpio node, and can1 has no phys property. CAN applications run on this board without an overlay.

mikroBUS Socket

The board provides the mikrobus_header GPIO nexus and the mikrobus_spi bus label, so SPI and GPIO shields under boards/shields can be built against the board directly:

west build -b kit_psc3m5_cc2 --shield mikroe_adc_click samples/basic/blinky

Header Pin Mapping

Index	Signal	Pin
0	AN	Not mapped
1	RST	Not mapped
2	CS	P5.3
3	SCK	P5.2
4	MISO	P5.1
5	MOSI	P5.0
6	PWM	P0.1
7	INT	P0.0
8	RX	P2.2
9	TX	P2.3
10	SCL	Not mapped
11	SDA	Not mapped

The AN pin is an analog net shared with potentiometer POT1 rather than a GPIO, and the RST pin is tied to 3V3 through a pull-up and not routed to the microcontroller. SCL and SDA are isolated from the microcontroller by unfitted 0 Ohm links, as described below. None of the four is present in the nexus. mikrobus_uart is not declared. P2.2 and P2.3 default to the isolated on-board debugger’s UART bridge, which is also the Zephyr console. A board-level switch can redirect them to the mikroBUS header instead, but doing so gives up the debug console, so the board devicetree keeps the factory default rather than modeling the header UART.

SPI

SCB3 serves the socket’s SPI signals:

Pin	SPI
P5.0	MOSI
P5.1	MISO
P5.2	CLK
P5.3	CS

The chip select is driven by the SCB rather than as a GPIO.

I2C is not available

The socket’s SCL and SDA pins are not connected to the microcontroller. The 0 Ohm links that would tie them to the SCB3 data lines are not fitted, so the pins terminate at the socket.

mikrobus_i2c is therefore not declared and nexus indices 10 and 11 are left unmapped, so an I2C shield fails to build rather than failing on hardware.

Analog Inputs

The HPPASS SAR ADC provides 28 channels: twelve directly sampled channels (0-11) followed by four muxed samplers of four channel slots each (12-15, 16-19, 20-23, 24-27). Sixteen dedicated analog pins feed them.

Channel	Pin	Net	Usage
0-2	AN_A0-A2	Motor 1 phase current U/V/W	Motor drive
3-4	AN_A3-A4	Motor 1 IDC / VDC link	Motor drive
5-7	AN_A5-A7	PFC IL0 / IL1 / Iac	PFC sense
8-10	AN_B0-B2	Motor 2 phase current U/V/W	Motor drive
11	AN_B3	Motor 2 IDC link	Motor drive
12	AN_B4	Vac0	Potentiometer POT1
16	AN_B5	Vac1	Potentiometer POT2
20	AN_B6	BrakeTemp1	Brake thermistor
24	AN_B7	Vbus PFC	PFC sense

Only channels 12 and 16 are user inputs. The remaining channels carry motor drive and PFC sense signals that reach the microcontroller through the power board connector.

Potentiometer POT1 shares its net with the mikroBUS AN pin, so a Click board that drives AN also affects the POT1 reading. POT2 is independent of the socket.

Power Board Connector

The pins not listed above are inverter gate-drive and power-stage enable signals for the two motors, routed to the power board connector. None of these outputs is enabled by the board devicetree; an application that needs one enables it from its own overlay.

Warning

Do not run an application that drives these pins while a power board is attached. Driving a high side signal and its matching low side signal together would shoot through the half bridge.

Building

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b kit_psc3m5_cc2 samples/hello_world

Programming and Debugging

The kit_psc3m5_cc2 board supports the runners and associated west commands listed below.

	flash	debug	attach	debugserver	rtt	reset
jlink	✅ (default)	✅ (default)	✅	✅	✅	✅

The KIT_PSC3M5_CC2 includes an onboard isolated SEGGER J-Link LITE programmer/debugger which can be used to program and debug the PSOC™ Control C3M5 Cortex®-M33 core. The SEGGER J-Link Software package must be installed on the host.

Configuring a Console

Connect a USB cable from your PC to the debug USB connector on the KIT_PSC3M5_CC2. Use the serial terminal of your choice (minicom, PuTTY, etc.) with the following settings:

Speed: 115200
Data: 8 bits
Parity: None
Stop bits: 1

Flashing

Build and flash the application:

west build -b kit_psc3m5_cc2 -p always samples/hello_world
west flash

You should see the following message on the console:

*** Booting Zephyr OS build vX.Y.Z ***
Hello World! kit_psc3m5_cc2

Debugging

# From the root of the zephyr repository
west build -b kit_psc3m5_cc2 samples/hello_world
west debug

Once the GDB console starts, you may set breakpoints and perform standard GDB debugging on the PSOC™ Control C3M5 Cortex®-M33 core.