QEMU Emulation for X86 / Lakemont CPU

Overview

The X86 Lakemont QEMU board configuration is used to emulate the Intel Lakemont (Minute IA) CPU as found in the Quark family of SoCs.

Unlike the Lakemont-based hardware targets, which have neither a BIOS nor ACPI, QEMU presents a PC-compatible machine, so this board configuration provides the following devices:

  • HPET

  • Advanced Programmable Interrupt Controller (APIC)

  • NS16550 UART

Hardware

Supported Features

The qemu_x86_lakemont board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

Programming and Debugging

The qemu_x86_lakemont board supports the runners and associated west commands listed below.

flash debug

Applications for the qemu_x86_lakemont board configuration can be built and run in the usual way for emulated boards (see Building an Application and Run an Application for more details).

Flashing

While this board is emulated and you can’t “flash” it, you can use this configuration to run basic Zephyr applications and kernel tests in the QEMU emulated environment. For example, with the Basic Synchronization sample:

# From the root of the zephyr repository
west build -b qemu_x86_lakemont samples/synchronization
west build -t run

Exit QEMU by pressing CTRL+A x.

Debugging

Refer to the detailed overview about Application Debugging.