RA4E1 Voice User Reference Kit

Overview

VOICE-RA4E1 is an edge voice recognition evaluation kit designed to be used by Ecosystem Partners, Application Engineers, Field Application Engineers, and for Business Development opportunities. The primary purpose is to evaluate the functionality of projects developed by Ecosystem Partners, and to facilitate the development of additional partner projects. The kit design to use the RA4E1 MCU with QFN 48pin package as the core logic device, with QSPI flash, OPAMP and power devices chosen from the Renesas product portfolio.

The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to 100 MHz with the following features:

MCU Native Pin Access

  • R7FA4E10D2CNE MCU (referred to as RA MCU)

  • 100 MHz, Arm® Cortex®-M33 core

  • 512 KB Code Flash, 8 KB Data Flash, 128 KB SRAM

  • 48 pins, LQFP package

  • MCU current measurement point for precision current consumption measurement

  • Multiple clock sources - Low-precision (~1%) clocks are available internal to the RA MCU.

Kit Peripheral Features

Following is a list of the specific features that have been implemented:

  • QSPI: One QSPI flash memory device, Dialog AT25SF641B-MHB-T, 64M-bit (8MB).

  • PMOD: 1 Digilent PMOD connectors, supporting UART, SPI and I2C configurations.

  • Microphones: 1 I2S MEMS digital microphones and 2 MEMS analog microphones, distance between each pair of microphones is 50mm which is suitable for beamforming applications.

  • Audio out: One stereo audio headphone jack supporting mono output on both channels.

  • LEDs: Five LEDs, D2 (Red), D3 (Green) and D4 (Blue) configurable by user, D5 (Blue) as a 3.3V power indicator, D8(Green) as a JLOB (J-LINK on board) indicator.

  • Buttons: One RESET button (S2), and one USER button (S1).

  • Debug: J-Link On-Board debug interface, supporting JTAG or SWD debug port.

  • USB: Micro USB-B (J6) for power input and J-Link On-Board function, USB-C (J1) for power input and RA4E1 USB Full Speed port as a USB device.

  • Form Factor: 7.5 x 6 cm

Hardware

Detailed hardware features can be found at:

Supported Features

The voice_ra4e1 board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

voice_ra4e1/r7fa4e10d2cne target

Type

Location

Description

Compatible

CPU

on-chip

ARM Cortex-M33 CPU1

arm,cortex-m33

ADC

on-chip

Renesas RA ADC node1

renesas,ra-adc

Clock control

on-chip

Renesas RA Clock Generation Circuit external clock configuration1

renesas,ra-cgc-external-clock

on-chip

Generic fixed-rate clock provider3

fixed-clock

on-chip

Renesas RA Sub-Clock1

renesas,ra-cgc-subclk

on-chip

Renesas RA Clock Generation Circuit PLL Clock2

renesas,ra-cgc-pll

on-chip

Renesas RA Clock Control node pclk block1

renesas,ra-cgc-pclk-block

on-chip

Renesas RA Clock Control Peripheral Clock7 1

renesas,ra-cgc-pclk

Counter

on-chip

Renesas RA AGT as Counter5

renesas,ra-agt-counter

DAC

on-chip

Renesas RA DAC Controller Global1

renesas,ra-dac-global

on-chip

Renesas RA DAC Controller1

renesas,ra-dac

Flash controller

on-chip

Renesas RA family flash high-performance controller1

renesas,ra-flash-hp-controller

GPIO & Headers

on-chip

Renesas RA GPIO I/O Port4 2

renesas,ra-gpio-ioport

I2C

on-chip

Renesas RA I2C Master controller1

renesas,ra-iic

Input

on-board

Group of GPIO-bound input keys1

gpio-keys

Interrupt controller

on-chip

ARMv8-M NVIC (Nested Vectored Interrupt Controller)1

arm,v8m-nvic

LED

on-board

Group of GPIO-controlled LEDs1

gpio-leds

Miscellaneous

on-chip

Renesas RA SCI controller1 3

renesas,ra-sci

on-chip

Renesas RA AGT5

renesas,ra-agt

on-chip

Renesas RA External Interrupt1 15

renesas,ra-external-interrupt

MMU / MPU

on-chip

ARMv8-M MPU (Memory Protection Unit)1

arm,armv8m-mpu

MTD

on-chip

Flash memory binding of Renesas RA family2

renesas,ra-nv-flash

on-board

Fixed partitions of a flash (or other non-volatile storage) memory1

fixed-partitions

PHY

on-chip

This binding is to be used by all the usb transceivers which are built-in with USB IP1

usb-nop-xceiv

Pin control

on-chip

The Renesas RA pin controller is a node responsible for controlling pin function selection and pin properties, such as routing a SCI0 RXD to P6101

renesas,ra-pinctrl-pfs

PWM

on-chip

Renesas RA Pulse Width Modulation4

renesas,ra-pwm

RNG

on-chip

Renesas RA SCE9 TRNG1

renesas,ra-sce9-rng

Serial controller

on-chip

Renesas RA SCI UART controller1 3

renesas,ra-sci-uart

SPI

on-chip

Renesas RA SPI controller1

renesas,ra-spi

SRAM

on-chip

Generic on-chip SRAM description1

mmio-sram

Timer

on-chip

ARMv8-M System Tick1

arm,armv8m-systick

USB

on-chip

Renesas RA USB full-speed controller1

renesas,ra-usbfs

on-chip

Renesas RA USB device controller1

renesas,ra-udc

Watchdog

on-chip

Renesas RA Watchdog (wdt)1

renesas,ra-wdt

Programming and Debugging

Applications for the voice_ra4e1 board can be built, flashed, and debugged in the usual way. See Building an Application and Run an Application for more details on building and running.

Flashing

Program can be flashed to VOICE-RA4E1 via the on-board SEGGER J-Link debugger. SEGGER J-link’s drivers are available at https://www.segger.com/downloads/jlink/

To flash the program to board

  1. Connect to J-Link OB via USB port to host PC

  2. Make sure J-Link OB jumper is in default configuration as describe in VOICE-RA4E1 - Engineering Manual

  3. Execute west command

    west flash -r jlink
    

Debugging

You can use Segger Ozone (Segger Ozone Download) for a visual debug interface

Once downloaded and installed, open Segger Ozone and configure the debug project like so:

  • Target Device: R7FA4E10D

  • Target Interface: SWD

  • Target Interface Speed: 4 MHz

  • Host Interface: USB

  • Program File: <path/to/your/build/zephyr.elf>

Note: It’s verified that we can debug OK on Segger Ozone v3.30d so please use this or later version of Segger Ozone

References