FRDM-IMX93
Overview
The FRDM-IMX93 board is a low-cost and compact platform designed to show the most commonly used features of the i.MX 93 Applications Processor in a small and low cost package. The FRDM-IMX93 board is an entry-level development board, which helps developers to get familiar with the processor before investing a large amount of resources in more specific designs.
i.MX93 MPU is composed of one cluster of 2x Cortex®-A55 cores and a single Cortex®-M33 core. Zephyr RTOS is ported on Cortex®-A55 core.
Hardware
i.MX 93 applications processor
The processor integrates up to two Arm Cortex-A55 cores, and supports built-in Arm Cortex-M33 core.
RAM: 2GB LPDDR4
Storage:
SanDisk 16GB eMMC5.1
microSD Socket
Wireless:
Murata Type-2EL (SDIO+UART+SPI) module. It is based on NXP IW612 SoC, which supports dual-band (2.4 GHz /5 GHz) 1x1 Wi-Fi 6, Bluetooth 5.2, and 802.15.4
USB:
One USB 2.0 Type C connector
One USB 2.0 Type A connector
Ethernet
PCI-E M.2
Connectors:
40-Pin Dual Row Header
LEDs:
1x Power status LED
1x RGB LED
Debug
JTAG 3-pin connector
USB-C port for UART debug, two COM ports for A55 and M33
Supported Features
The frdm_imx93 board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
frdm_imx93/mimx9352/a55 target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
||
CAN |
on-chip |
||
Clock control |
on-chip |
i.MX CCM Rev2 (Clock Controller Module) IP node1 |
|
Counter |
on-chip |
NXP Timer/PWM Module (TPM) used as timer6 |
|
DAI |
on-chip |
NXP Synchronous Audio Interface (SAI)1 |
|
DMA |
on-chip |
NXP enhanced Direct Memory Access (eDMA)1 |
|
Ethernet |
on-chip |
NXP ENET1G IP Module1 |
|
on-chip |
NXP ENET MAC/L2 Device1 |
||
on-chip |
NXP ENET PTP (Precision Time Protocol) Clock1 |
||
GPIO & Headers |
on-chip |
i.MX RGPIO4 |
|
on-board |
NXP PCAL6524 I2C GPIO expander1 |
||
I2C |
on-chip |
||
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARM Generic Interrupt Controller v31 |
|
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
MDIO |
on-chip |
NXP ENET MDIO Features1 |
|
PHY |
on-board |
Simple GPIO controlled CAN transceiver1 |
|
Pin control |
on-chip |
This compatible binding should be applied to the device’s iomuxc DTS node1 |
|
on-chip |
The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1 |
||
Power management CPU operations |
on-chip |
Power State Coordination Interface (PSCI) version 1.11 |
|
SDHC |
on-chip |
NXP imx USDHC controller2 |
|
Serial controller |
on-chip |
||
SPI |
on-chip |
NXP LPSPI controller8 |
|
Timer |
on-chip |
per-core ARM architected timer1 |
Devices
System Clock
This board configuration uses a system clock frequency of 24 MHz. Cortex-A55 Core runs up to 1.7 GHz. Cortex-M33 Core runs up to 200MHz in which SYSTICK runs on same frequency.
Serial Port
This board configuration uses a single serial communication channel with the CPU’s UART2 for A55 core and M33 core.
Programming and Debugging (A55)
U-Boot “cpu” command is used to load and kick Zephyr to Cortex-A secondary Core, Currently it is supported in : Real-Time Edge U-Boot (use the branch “uboot_vxxxx.xx-y.y.y, xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example “uboot_v2023.04-2.9.0” branch is U-Boot v2023.04 used in Real-Time Edge Software release v2.9.0), and pre-build images and user guide can be found at Real-Time Edge Software.
Copy the compiled zephyr.bin to the first FAT partition of the SD card and
plug the SD card into the board. Power it up and stop the u-boot execution at
prompt.
Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1:
fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; cpu 1 release 0xd0000000
Or use the following command to kick zephyr.bin to Cortex-A55 Core0:
fatload mmc 1:1 0xd0000000 zephyr.bin; dcache off; icache flush; go 0xd0000000
Use this configuration to run basic Zephyr applications and kernel tests, for example, with the Basic Synchronization sample:
# From the root of the zephyr repository
west build -b frdm_imx93/mimx9352/a55 samples/synchronization
This will build an image with the synchronization sample app, boot it and display the following console output:
*** Booting Zephyr OS build v4.1.0-41-g6395333e3d18 ***
thread_a: Hello World from cpu 0 on frdm_imx93!
thread_b: Hello World from cpu 0 on frdm_imx93!
thread_a: Hello World from cpu 0 on frdm_imx93!
thread_b: Hello World from cpu 0 on frdm_imx93!
System Reboot (A55)
Currently i.MX93 only support cold reboot and doesn’t support warm reboot. Use this configuratiuon to verify cold reboot with Custom Shell module sample:
# From the root of the zephyr repository
west build -b frdm_imx93/mimx9352/a55 samples/subsys/shell/shell_module
This will build an image with the shell sample app, boot it and execute kernel reboot command in shell command line:
uart:~$ kernel reboot cold
Support Resources for Zephyr
MCUXpresso for VS Code, wiki documentation and Zephyr lab guides
NXP’s Zephyr landing page (including training resources)