LPC845-BRK

Overview

The LPC845 Breakout Board, developed by NXP, enables rapid evaluation and prototyping with the LPC84x family of microcontrollers.

The LPC84x family is based on the Arm® Cortex®-M0+ architecture and is a low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. It supports up to 64 KB of Flash memory and 16 KB of SRAM, along with a flexible peripheral configuration using a switch matrix.

Hardware

The LPC845-BRK board is based on the NXP LPC845 MCU and provides:

  • Arm Cortex-M0+ CPU running at up to 30 MHz

  • 64 KB on-chip Flash and 16 KB SRAM

  • Internal Free Running Oscillator (FRO) with multiple frequency options

  • 5x USART interfaces with switch matrix routing and fractional baud rate

  • 2x SPI controllers with switch matrix routing

  • 4x I2C interfaces (one supporting Fast-mode Plus at 1 Mbit/s)

  • One 12-bit ADC and two 10-bit DACs

  • SCTimer/PWM and multiple general-purpose timers

  • 25-channel DMA controller and CRC engine

  • Up to 54 GPIOs with flexible switch matrix configuration

  • Pin interrupts and Pattern match engine support on up to eight pins (irq slots)

  • Serial Wire Debug (SWD) interface

  • Capacitive Touch Interface

The lpc845brk board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

lpc845brk/lpc845 target

On-target memory for this board target: 16 KiB of RAM, 64 KiB of Flash.

Type

Location

Description

Compatible

CPU

on-chip

ARM Cortex-M0+ CPU1

arm,cortex-m0+

Clock control

on-chip

NXP LPC84x Clock Controller1

nxp,lpc84x-clock

Flash controller

on-chip

NXP LPC84x on chip flash controller (ROM IAP, FMC)1

nxp,iap-fmc84x

Interrupt controller

on-chip

ARMv6-M NVIC (Nested Vectored Interrupt Controller) controller1

arm,v6m-nvic

MTD

on-chip

Flash node1

soc-nv-flash

Pin control

on-chip

NXP LPC84x Switch Matrix Pin Controller1

nxp,lpc84x-swm

on-chip

NXP LPC84x IOCON Pin Controller1

nxp,lpc84x-iocon

Serial controller

on-chip

NXP LPC84x UART14

nxp,lpc84x-uart

SRAM

on-chip

Generic on-chip SRAM1

mmio-sram

Timer

on-chip

ARMv6-M System Tick1

arm,armv6m-systick

Connections and IOs

The LPC845 uses a switch matrix (SWM) and an IOCON block to configure pin functions.

Default pin configuration:

Name

Function

Usage

PIO0_24

UART0 TXD

Console TX

PIO0_25

UART0 RXD

Console RX

PIO1_0

GPIO

GREEN LED

PIO1_1

GPIO

BLUE LED

PIO1_2

GPIO

RED LED

PIO0_11

I2C

I2C0 SDA

PIO0_10

I2C

I2C0 SCL

PIO0_31

CAPT

CAPT_X0

PIO1_8

CAPT

CAPT_YL

PIO1_9

CAPT

CAPT_YH

PIO0_2

SWD

SWD Debug Port

PIO0_3

SWD

SWD Debug Port

PIO0_4

GPIO

User SW

PIO0_5

GPIO

Reset SW

PIO0_7

ADC

Potentiometer

PIO0_12

GPIO

ISP Booting SW

Note

The LPC845 Switch Matrix (SWM) allows highly flexible pin routing. While the above table lists default and fixed-pin connections, movable functions (e.g., SPI, PWM, USART) can be routed to almost any available GPIO pin via devicetree configuration.

Programming and Debugging

The lpc845brk board supports the runners and associated west commands listed below.

flash debug rtt attach debugserver
pyocd ✅ (default) ✅ (default) ✅ ✅ ✅

Building

Here is an example for building the Hello World sample application.

# From the root of the zephyr repository
west build -b lpc845brk samples/hello_world

Flashing

Once the application is built, you can flash it using:

west flash

Debugging

To debug the application:

west debug

References

Support Resources for Zephyr