MR-NavQ95B

Overview

The NXP MR-NAVQ95 [8] is an open-source development board designed for mobile robotics applications. It is based on the NXP i.MX95 applications processor and provides heterogeneous multicore processing capabilities suitable for combining real-time workloads with high-performance application processing.

The platform integrates Cortex-A55 application cores alongside Cortex-M7 and Cortex-M33 real-time cores. In Zephyr, support is currently focused on the Cortex-M7 core, which is typically the target for real-time firmware.

Hardware

Processor

NXP i.MX95 SoC
- 6x Arm Cortex-A55 cores
- 1x Arm Cortex-M7 core
- 1x Arm Cortex-M33 core

Memory

On-chip SRAM: 1376 KiB (ECC)
External LPDDR5: 16 GiB (with inline ECC and encryption)
External Flash: 64 MiB Octal SPI NOR

Supported Features

The mr_navq95b board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`mr_navq95b/mimx9596/m7` target

On-target memory for this board target: 256 KiB of RAM, 256 KiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M7 CPU1	`arm,cortex-m7`
ADC	on-chip	NXP successive-approximation ADC (SAR ADC) controller1	`nxp,sar-adc`
ARM architecture	on-chip	i.MX DTCM (Data Tightly Coupled Memory)1	`nxp,imx-dtcm`
CAN	on-chip	NXP FlexCAN CANFD controller2 3	`nxp,flexcan-fd`
Counter	on-chip	NXP LPTMR2	`nxp,lptmr`
	on-chip	NXP Low Power Periodic Interrupt Timer (LPIT)2	`nxp,lpit`
	on-chip	Child node for the Low Power Periodic Interrupt Timer node, intended for an individual timer channel8	`nxp,lpit-channel`
DAI	on-chip	NXP Synchronous Audio Interface (SAI)1	`nxp,dai-sai`
Display	on-chip	socionext DPU display controller for DSI panels1	`socionext,dpu`
DMA	on-chip	NXP MCUX EDMA controller2	`nxp,mcux-edma`
Ethernet	on-chip	NXP i.MX NETC Block Controller1	`nxp,imx-netc-blk-ctrl`
	on-chip	NXP i.MX NETC Controller1	`nxp,imx-netc`
	on-chip	NXP i.MX NETC Physical Station Interface (PSI)3	`nxp,imx-netc-psi`
	on-chip	NXP i.MX NETC External MDIO controller1	`nxp,imx-netc-emdio`
	on-chip	NXP NETC PTP (Precision Time Protocol) Clock1	`nxp,netc-ptp-clock`
Firmware	on-chip	SCMI (System Control and Management Interface) SHMEM (shared memory)1	`arm,scmi-shmem`
	on-chip	SCMI (System Control and Management Interface) with doorbell and SHMEM (shared memory) transport1	`arm,scmi`
	on-chip	SCMI (System Control and Management Interface) power domain protocol1	`arm,scmi-power`
	on-chip	SCMI (System Control and Management Interface) system power protocol1	`arm,scmi-system`
	on-chip	SCMI (System Control and Management Interface) clock protocol1	`arm,scmi-clock`
	on-chip	SCMI (System Control and Management Interface) pinctrl protocol1	`arm,scmi-pinctrl`
	on-chip	SCMI (System Control and Management Interface) cpu domain protocol1	`nxp,scmi-cpu`
GPIO & Headers	on-chip	i.MX RGPIO2 3	`nxp,imx-rgpio`
I2C	on-chip	NXP LPI2C controller1 7	`nxp,lpi2c`
I2S	on-chip	NXP mcux SAI-I2S controller1	`nxp,mcux-i2s`
I3C	on-chip	NXP MCUX I3C controller1 1	`nxp,mcux-i3c`
Interrupt controller	on-chip	ARMv7-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v7m-nvic`
	on-chip	i.MX DSP interrupt controller1 1	`nxp,irqsteer-intc`
	on-chip	i.MX IRQ_STEER master10 6	`nxp,irqsteer-master`
Mailbox	on-chip	NXP i.MX Message Unit as Zephyr MBOX1 1	`nxp,mbox-imx-mu`
MIPI-DSI	on-chip	NXP MCUX MIPI DSI DWC1	`nxp,mipi-dsi-dwc`
Miscellaneous	on-chip	NXP FlexIO controller2	`nxp,flexio`
MMU / MPU	on-chip	ARMv7-M Memory Protection Unit (MPU)1	`arm,armv7m-mpu`
MTD	on-board	NXP FlexSPI MX25UM51345G1	`nxp,imx-flexspi-mx25um51345g`
MTD	on-board	Flash node1	`soc-nv-flash`
Pin control	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	`nxp,imx93-pinctrl`
Power domain	on-chip	SCMI (System Control and Management Interface) power domain2	`arm,scmi-power-domain`
PWM	on-chip	MCUX Timer/PWM Module (TPM)3 3	`nxp,kinetis-tpm`
Sensors	on-board	BMI08X Accel inertial measurement unit1	`bosch,bmi08x-accel`
	on-board	BMI08X Gyro inertial measurement unit1	`bosch,bmi08x-gyro`
	on-board	ICM45686 High-precision 6-axis motion tracking device When setting the accel-pm, accel-range, accel-odr, gyro-pm, gyro-range, gyro-odr properties in a .dts or .dtsi file you may include icm45686.h and use the macros defined there1	`invensense,icm45686`
	on-board	The BMP581 is a Barometric pressure sensor on I3C1	`bosch,bmp581`
	on-board	Bosch BMM350 Geomagnetic sensor1	`bosch,bmm350`
Serial controller	on-chip	NXP LPUART2 6	`nxp,lpuart`
SPI	on-chip	NXP FlexSPI controller1	`nxp,imx-flexspi`
SPI	on-chip	NXP LPSPI controller2 6	`nxp,lpspi`
Timer	on-chip	ARMv7-M System Tick1	`arm,armv7m-systick`
Watchdog	on-chip	NXP watchdog (WDOG32)1	`nxp,wdog32`

`mr_navq95b/mimx9596/m7/ddr` target

On-target memory for this board target: 4 MiB of RAM, N/A of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M7 CPU1	`arm,cortex-m7`
ADC	on-chip	NXP successive-approximation ADC (SAR ADC) controller1	`nxp,sar-adc`
ARM architecture	on-chip	i.MX DTCM (Data Tightly Coupled Memory)1	`nxp,imx-dtcm`
CAN	on-chip	NXP FlexCAN CANFD controller2 3	`nxp,flexcan-fd`
Counter	on-chip	NXP LPTMR2	`nxp,lptmr`
	on-chip	NXP Low Power Periodic Interrupt Timer (LPIT)2	`nxp,lpit`
	on-chip	Child node for the Low Power Periodic Interrupt Timer node, intended for an individual timer channel8	`nxp,lpit-channel`
DAI	on-chip	NXP Synchronous Audio Interface (SAI)1	`nxp,dai-sai`
Display	on-chip	socionext DPU display controller for DSI panels1	`socionext,dpu`
DMA	on-chip	NXP MCUX EDMA controller2	`nxp,mcux-edma`
Ethernet	on-chip	NXP i.MX NETC Block Controller1	`nxp,imx-netc-blk-ctrl`
	on-chip	NXP i.MX NETC Controller1	`nxp,imx-netc`
	on-chip	NXP i.MX NETC Physical Station Interface (PSI)3	`nxp,imx-netc-psi`
	on-chip	NXP i.MX NETC External MDIO controller1	`nxp,imx-netc-emdio`
	on-chip	NXP NETC PTP (Precision Time Protocol) Clock1	`nxp,netc-ptp-clock`
Firmware	on-chip	SCMI (System Control and Management Interface) SHMEM (shared memory)1	`arm,scmi-shmem`
	on-chip	SCMI (System Control and Management Interface) with doorbell and SHMEM (shared memory) transport1	`arm,scmi`
	on-chip	SCMI (System Control and Management Interface) power domain protocol1	`arm,scmi-power`
	on-chip	SCMI (System Control and Management Interface) system power protocol1	`arm,scmi-system`
	on-chip	SCMI (System Control and Management Interface) clock protocol1	`arm,scmi-clock`
	on-chip	SCMI (System Control and Management Interface) pinctrl protocol1	`arm,scmi-pinctrl`
	on-chip	SCMI (System Control and Management Interface) cpu domain protocol1	`nxp,scmi-cpu`
GPIO & Headers	on-chip	i.MX RGPIO2 3	`nxp,imx-rgpio`
I2C	on-chip	NXP LPI2C controller1 7	`nxp,lpi2c`
I2S	on-chip	NXP mcux SAI-I2S controller1	`nxp,mcux-i2s`
I3C	on-chip	NXP MCUX I3C controller1 1	`nxp,mcux-i3c`
Interrupt controller	on-chip	ARMv7-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v7m-nvic`
	on-chip	i.MX DSP interrupt controller1 1	`nxp,irqsteer-intc`
	on-chip	i.MX IRQ_STEER master10 6	`nxp,irqsteer-master`
Mailbox	on-chip	NXP i.MX Message Unit as Zephyr MBOX1 1	`nxp,mbox-imx-mu`
MIPI-DSI	on-chip	NXP MCUX MIPI DSI DWC1	`nxp,mipi-dsi-dwc`
Miscellaneous	on-chip	NXP FlexIO controller2	`nxp,flexio`
MMU / MPU	on-chip	ARMv7-M Memory Protection Unit (MPU)1	`arm,armv7m-mpu`
MTD	on-board	NXP FlexSPI MX25UM51345G1	`nxp,imx-flexspi-mx25um51345g`
MTD	on-board	Flash node1	`soc-nv-flash`
Pin control	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	`nxp,imx93-pinctrl`
Power domain	on-chip	SCMI (System Control and Management Interface) power domain2	`arm,scmi-power-domain`
PWM	on-chip	MCUX Timer/PWM Module (TPM)3 3	`nxp,kinetis-tpm`
Sensors	on-board	BMI08X Accel inertial measurement unit1	`bosch,bmi08x-accel`
	on-board	BMI08X Gyro inertial measurement unit1	`bosch,bmi08x-gyro`
	on-board	ICM45686 High-precision 6-axis motion tracking device When setting the accel-pm, accel-range, accel-odr, gyro-pm, gyro-range, gyro-odr properties in a .dts or .dtsi file you may include icm45686.h and use the macros defined there1	`invensense,icm45686`
	on-board	The BMP581 is a Barometric pressure sensor on I3C1	`bosch,bmp581`
	on-board	Bosch BMM350 Geomagnetic sensor1	`bosch,bmm350`
Serial controller	on-chip	NXP LPUART2 6	`nxp,lpuart`
SPI	on-chip	NXP FlexSPI controller1	`nxp,imx-flexspi`
SPI	on-chip	NXP LPSPI controller2 6	`nxp,lpspi`
Timer	on-chip	ARMv7-M System Tick1	`arm,armv7m-systick`
Watchdog	on-chip	NXP watchdog (WDOG32)1	`nxp,wdog32`

`mr_navq95b/mimx9596/m7/flash` target

On-target memory for this board target: 256 KiB of RAM, 64 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M7 CPU1	`arm,cortex-m7`
ADC	on-chip	NXP successive-approximation ADC (SAR ADC) controller1	`nxp,sar-adc`
ARM architecture	on-chip	i.MX DTCM (Data Tightly Coupled Memory)1	`nxp,imx-dtcm`
CAN	on-chip	NXP FlexCAN CANFD controller2 3	`nxp,flexcan-fd`
Counter	on-chip	NXP LPTMR2	`nxp,lptmr`
	on-chip	NXP Low Power Periodic Interrupt Timer (LPIT)2	`nxp,lpit`
	on-chip	Child node for the Low Power Periodic Interrupt Timer node, intended for an individual timer channel8	`nxp,lpit-channel`
DAI	on-chip	NXP Synchronous Audio Interface (SAI)1	`nxp,dai-sai`
Display	on-chip	socionext DPU display controller for DSI panels1	`socionext,dpu`
DMA	on-chip	NXP MCUX EDMA controller2	`nxp,mcux-edma`
Ethernet	on-chip	NXP i.MX NETC Block Controller1	`nxp,imx-netc-blk-ctrl`
	on-chip	NXP i.MX NETC Controller1	`nxp,imx-netc`
	on-chip	NXP i.MX NETC Physical Station Interface (PSI)3	`nxp,imx-netc-psi`
	on-chip	NXP i.MX NETC External MDIO controller1	`nxp,imx-netc-emdio`
	on-chip	NXP NETC PTP (Precision Time Protocol) Clock1	`nxp,netc-ptp-clock`
Firmware	on-chip	SCMI (System Control and Management Interface) SHMEM (shared memory)1	`arm,scmi-shmem`
	on-chip	SCMI (System Control and Management Interface) with doorbell and SHMEM (shared memory) transport1	`arm,scmi`
	on-chip	SCMI (System Control and Management Interface) power domain protocol1	`arm,scmi-power`
	on-chip	SCMI (System Control and Management Interface) system power protocol1	`arm,scmi-system`
	on-chip	SCMI (System Control and Management Interface) clock protocol1	`arm,scmi-clock`
	on-chip	SCMI (System Control and Management Interface) pinctrl protocol1	`arm,scmi-pinctrl`
	on-chip	SCMI (System Control and Management Interface) cpu domain protocol1	`nxp,scmi-cpu`
GPIO & Headers	on-chip	i.MX RGPIO2 3	`nxp,imx-rgpio`
I2C	on-chip	NXP LPI2C controller1 7	`nxp,lpi2c`
I2S	on-chip	NXP mcux SAI-I2S controller1	`nxp,mcux-i2s`
I3C	on-chip	NXP MCUX I3C controller1 1	`nxp,mcux-i3c`
Interrupt controller	on-chip	ARMv7-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v7m-nvic`
	on-chip	i.MX DSP interrupt controller1 1	`nxp,irqsteer-intc`
	on-chip	i.MX IRQ_STEER master10 6	`nxp,irqsteer-master`
Mailbox	on-chip	NXP i.MX Message Unit as Zephyr MBOX1 1	`nxp,mbox-imx-mu`
MIPI-DSI	on-chip	NXP MCUX MIPI DSI DWC1	`nxp,mipi-dsi-dwc`
Miscellaneous	on-chip	NXP FlexIO controller2	`nxp,flexio`
MMU / MPU	on-chip	ARMv7-M Memory Protection Unit (MPU)1	`arm,armv7m-mpu`
MTD	on-board	NXP FlexSPI MX25UM51345G1	`nxp,imx-flexspi-mx25um51345g`
MTD	on-board	Flash node1	`soc-nv-flash`
Pin control	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	`nxp,imx93-pinctrl`
Power domain	on-chip	SCMI (System Control and Management Interface) power domain2	`arm,scmi-power-domain`
PWM	on-chip	MCUX Timer/PWM Module (TPM)3 3	`nxp,kinetis-tpm`
Sensors	on-board	BMI08X Accel inertial measurement unit1	`bosch,bmi08x-accel`
	on-board	BMI08X Gyro inertial measurement unit1	`bosch,bmi08x-gyro`
	on-board	ICM45686 High-precision 6-axis motion tracking device When setting the accel-pm, accel-range, accel-odr, gyro-pm, gyro-range, gyro-odr properties in a .dts or .dtsi file you may include icm45686.h and use the macros defined there1	`invensense,icm45686`
	on-board	The BMP581 is a Barometric pressure sensor on I3C1	`bosch,bmp581`
	on-board	Bosch BMM350 Geomagnetic sensor1	`bosch,bmm350`
Serial controller	on-chip	NXP LPUART2 6	`nxp,lpuart`
SPI	on-chip	NXP FlexSPI controller1	`nxp,imx-flexspi`
SPI	on-chip	NXP LPSPI controller2 6	`nxp,lpspi`
Timer	on-chip	ARMv7-M System Tick1	`arm,armv7m-systick`
Watchdog	on-chip	NXP watchdog (WDOG32)1	`nxp,wdog32`

Connectivity

The NXP MR-NAVQ95 [8] consists of a base board which can be extended with optional add-on modules for additional interfaces and functionality. This block diagram [10] provides an overview of the extension boards and the peripherals that are available for use.

These interfaces are multiplexed and depend on board configuration and pinmux settings of the i.MX95 platform.

Serial Console

The default serial console is routed to UART2 interface. It can be accessed through a USB-to_UART bridge on the USB-C connector (J10) on the I/O expansion board. Alternatively, UART2 is also available on a dedicated JST-GH board connector (J2) on the main board.

Build and run Hello World

It is recommended to have the NavQ95 image installed on the SD-card. This will initialise the M33 and the A55 cores and allows to run the zephyr firmware from external flash by running MCUBoot on the M7 at startup. Build and download instructions for this SD-card image can be found on NXP IMX-MANIFEST-NAVQ95 [9]

To build a Zephyr application for the MR-NAVQ95B on ITCM:

west build -b mr_navq95b/mimx9596/m7 samples/hello_world/

To build the application to run from the MX25UM51345G external flash:

west build -b mr_navq95b/mimx9596/m7/flash samples/hello_world/

Uploading the binary can be performed using a Segger/J-Link probe connected to port J7:

west flash

Note

You need to have support for the mimx95_cm7_mx25um target in PyOCD to flash the binary onto the external flash. At the time of writing this support is not yet pulled in.

Follow this procedure to get PyOCD with support for mimx95_cm7_mx25um:

Install pyocd to flash the image through the on-board JTAG device.
Clone pyocd into a directory of your preference and checkout the pr-imx95 branch:
```
git clone https://github.com/NXP-Robotics/pyOCD -b pr-imx95
```

Build pyocd:

cd pyocd-private
python3 -m pip install .

When running the firmware from external flash, the standard boot flow involves:

System Manager (Cortex-M33) initializes the system
MCUBoot is loaded into TCM
MCUBoot validates firmware in external flash
Firmware executes from flash (XIP)

Support Resources for Zephyr

NXP Board Support Status [1]
NXP Zephyr Downstream Software Development Kit [2]
MCUXpresso for VS Code documentation [3], and Zephyr lab guides [4]
NXP Zephyr Knowledge Hub [5]
NXP’s Zephyr landing page [6] (including training resources)
NXP Support Community forum for Zephyr [7]