FRDM-iMXRT1186

Overview

NXP FRDM-IMXRT1186 is a cost-effective development board based on NXP’s i.MX RT1186 crossover MCU, combining high performance with real-time capabilities. Easy I/O access supports expansion boards for fast prototyping and rapid evaluation of Programmable Logic Controllers, Remote IOs, motor control and other industrial automation applications.

Hardware

i.MX RT1186 Crossover Processor:
- 800 MHz Arm Cortex-M7 core
- 300 MHz Arm Cortex-M33 core
- First real-time microcontroller (MCU) with an integrated Gbps time-sensitive network (TSN) switch supporting multiple protocols bridging communications between existing systems and Industry 4.0
- First crossover MCU with an integrated EdgeLock® Secure Enclave
- Up to 1.5 MB SRAM (ECC protected) with 512 KB of TCM for Arm Cortex-M7 and 256 KB of TCM for Arm Cortex-M33
Board Memory
- 256 Mbit HyperRAM memory
- 512 Mbit HyperFlash
- 128 Mbit QSPI Flash
Connectivity
- 2x Ethernet (10/100/1000M) connectors for TSN switch
- 2x Ethernet (10/100M) connectors for EtherCAT or TSN switch
- 1x Type-C USB OTG connector
- 1x CAN transceivers
Debug Capabilities
- JTAG connector
- On-board MCU-Link debugger
Expansion Connectors
- ARDUINO® UNO R3 header
- FRDM header
- FlexSPI Follower header
- SRAMC header
- Motor header

For more information about the i.MX RT1186 SoC and FRDM-iMXRT1186 board, see:

Supported Features

The FRDM-iMXRT1186 board is a cost-effective development platform. NXP considers the MIMXRT1180-EVK as the superset board for the i.MX RT118x family of MCUs. The MIMXRT1180-EVK is the focus for NXP’s Full Platform Support for Zephyr, to better enable the entire RT118x family. NXP prioritizes enabling the MIMXRT1180-EVK with new support for Zephyr features. Some features may be limited or unavailable on the FRDM-iMXRT1186 compared to the MIMXRT1180-EVK.

The frdm_imxrt1186 board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`frdm_imxrt1186/mimxrt1186/cm33` target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33F CPU1	`arm,cortex-m33f`
ADC	on-chip	LPC LPADC2	`nxp,lpc-lpadc`
CAN	on-chip	NXP FlexCAN CANFD controller3	`nxp,flexcan-fd`
Clock control	on-chip	i.MX ANATOP (Analog Clock Controller Module) IP node1	`nxp,imx-anatop`
	on-chip	i.MX CCM Rev2 (Clock Controller Module) IP node1	`nxp,imx-ccm-rev2`
	on-chip	Generic fixed-rate clock provider2	`fixed-clock`
Comparator	on-chip	NXP Kinetis ACMP (Analog CoMParator)4	`nxp,kinetis-acmp`
Counter	on-chip	NXP MCUX General-Purpose Timer (GPT)1 1	`nxp,imx-gpt`
	on-chip	NXP MCUX Quad Timer (QTMR)8	`nxp,imx-qtmr`
	on-chip	NXP MCUX Quad Timer Channel32	`nxp,imx-tmr`
	on-chip	NXP Low Power Periodic Interrupt Timer (LPIT)3	`nxp,lpit`
	on-chip	Child node for the Low Power Periodic Interrupt Timer node, intended for an individual timer channel12	`nxp,lpit-channel`
	on-chip	NXP LPTMR3	`nxp,lptmr`
DAC	on-chip	NXP MCUX DAC121	`nxp,dac12`
DMA	on-chip	NXP MCUX EDMA controller2	`nxp,mcux-edma`
DSA	on-chip	NXP NETC ethernet switch1	`nxp,netc-switch`
Ethernet	on-chip	NXP i.MX NETC Controller1	`nxp,imx-netc`
	on-chip	NXP i.MX NETC Physical Station Interface (PSI)2	`nxp,imx-netc-psi`
	on-chip	NXP NETC PTP (Precision Time Protocol) Clock1	`nxp,netc-ptp-clock`
	on-chip	NXP i.MX NETC External MDIO controller1	`nxp,imx-netc-emdio`
GPIO & Headers	on-chip	i.MX RGPIO6	`nxp,imx-rgpio`
Hardware information	on-chip	NXP SRC REV2 get reset cause flags1	`nxp,imx-src-rev2`
I2C	on-chip	NXP LPI2C controller6	`nxp,lpi2c`
I2S	on-chip	NXP mcux SAI-I2S controller4	`nxp,mcux-i2s`
I3C	on-chip	NXP MCUX I3C controller2	`nxp,mcux-i3c`
Input	on-chip	NXP KPP controller1	`nxp,mcux-kpp`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v8m-nvic`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
Mailbox	on-chip	NXP i.MX Message Unit as Zephyr MBOX2	`nxp,mbox-imx-mu`
Miscellaneous	on-chip	NXP FlexIO controller2	`nxp,flexio`
MMU / MPU	on-chip	ARMv8-M MPU (Memory Protection Unit)1	`arm,armv8m-mpu`
MTD	on-board	NXP FlexSPI NOR1	`nxp,imx-flexspi-nor`
MTD	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	`fixed-partitions`
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	`nxp,imx-iomuxc`
	on-chip	The node has the ‘pinctrl’ node label set in MCUX RT SoC’s devicetree1	`nxp,mcux-rt11xx-pinctrl`
	on-chip	The node has the ‘pinctrl’ node label set in MCUX RT SoC’s devicetree1	`nxp,mcux-rt-pinctrl`
	on-chip	i.MX BLK CTRL NS AONMIX1	`nxp,imx-blkctrl-ns-aon`
	on-chip	i.MX BLK CTRL WAKEUP1	`nxp,imx-blkctrl-wakeup`
PWM	on-chip	NXP eFLEX PWM module with mcux-pwm submodules4	`nxp,flexpwm`
	on-chip	NXP MCUX PWM16	`nxp,imx-pwm`
	on-chip	MCUX Timer/PWM Module (TPM)6	`nxp,kinetis-tpm`
SDHC	on-chip	NXP imx USDHC controller2	`nxp,imx-usdhc`
Sensors	on-chip	NXP TMPSNS1	`nxp,tmpsns`
Serial controller	on-chip	NXP LPUART1 11	`nxp,lpuart`
SPI	on-chip	NXP LPSPI controller6	`nxp,lpspi`
SPI	on-chip	NXP FlexSPI controller1 1	`nxp,imx-flexspi`
Timer	on-chip	ARMv8-M System Tick1	`arm,armv8m-systick`
USB	on-chip	NXP EHCI USB device mode2	`nxp,ehci`
USB	on-chip	NXP USB High Speed PHY2	`nxp,usbphy`
Watchdog	on-chip	NXP External Watchdog Monitor1	`nxp,ewm`
Watchdog	on-chip	NXP RT watchdog1 4	`nxp,rtwdog`

`frdm_imxrt1186/mimxrt1186/cm7` target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M7 CPU1	`arm,cortex-m7`
ADC	on-chip	LPC LPADC2	`nxp,lpc-lpadc`
CAN	on-chip	NXP FlexCAN CANFD controller3	`nxp,flexcan-fd`
Clock control	on-chip	i.MX ANATOP (Analog Clock Controller Module) IP node1	`nxp,imx-anatop`
	on-chip	i.MX CCM Rev2 (Clock Controller Module) IP node1	`nxp,imx-ccm-rev2`
	on-chip	Generic fixed-rate clock provider2	`fixed-clock`
Comparator	on-chip	NXP Kinetis ACMP (Analog CoMParator)4	`nxp,kinetis-acmp`
Counter	on-chip	NXP MCUX General-Purpose Timer (GPT)1 1	`nxp,imx-gpt`
	on-chip	NXP MCUX Quad Timer (QTMR)8	`nxp,imx-qtmr`
	on-chip	NXP MCUX Quad Timer Channel32	`nxp,imx-tmr`
	on-chip	NXP Low Power Periodic Interrupt Timer (LPIT)3	`nxp,lpit`
	on-chip	Child node for the Low Power Periodic Interrupt Timer node, intended for an individual timer channel12	`nxp,lpit-channel`
	on-chip	NXP LPTMR3	`nxp,lptmr`
DAC	on-chip	NXP MCUX DAC121	`nxp,dac12`
DMA	on-chip	NXP MCUX EDMA controller2	`nxp,mcux-edma`
DSA	on-chip	NXP NETC ethernet switch1	`nxp,netc-switch`
Ethernet	on-chip	NXP i.MX NETC Controller1	`nxp,imx-netc`
	on-chip	NXP i.MX NETC Physical Station Interface (PSI)2	`nxp,imx-netc-psi`
	on-chip	NXP NETC PTP (Precision Time Protocol) Clock1	`nxp,netc-ptp-clock`
	on-chip	NXP i.MX NETC External MDIO controller1	`nxp,imx-netc-emdio`
GPIO & Headers	on-chip	i.MX RGPIO6	`nxp,imx-rgpio`
Hardware information	on-chip	NXP SRC REV2 get reset cause flags1	`nxp,imx-src-rev2`
I2C	on-chip	NXP LPI2C controller6	`nxp,lpi2c`
I2S	on-chip	NXP mcux SAI-I2S controller4	`nxp,mcux-i2s`
I3C	on-chip	NXP MCUX I3C controller2	`nxp,mcux-i3c`
Input	on-chip	NXP KPP controller1	`nxp,mcux-kpp`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	ARMv7-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v7m-nvic`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
Mailbox	on-chip	NXP i.MX Message Unit as Zephyr MBOX2	`nxp,mbox-imx-mu`
Miscellaneous	on-chip	NXP FlexIO controller2	`nxp,flexio`
MMU / MPU	on-chip	ARMv7-M Memory Protection Unit (MPU)1	`arm,armv7m-mpu`
MTD	on-board	NXP FlexSPI NOR1	`nxp,imx-flexspi-nor`
MTD	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	`fixed-partitions`
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	`nxp,imx-iomuxc`
	on-chip	The node has the ‘pinctrl’ node label set in MCUX RT SoC’s devicetree1	`nxp,mcux-rt11xx-pinctrl`
	on-chip	The node has the ‘pinctrl’ node label set in MCUX RT SoC’s devicetree1	`nxp,mcux-rt-pinctrl`
	on-chip	i.MX BLK CTRL NS AONMIX1	`nxp,imx-blkctrl-ns-aon`
	on-chip	i.MX BLK CTRL WAKEUP1	`nxp,imx-blkctrl-wakeup`
PWM	on-chip	NXP eFLEX PWM module with mcux-pwm submodules4	`nxp,flexpwm`
	on-chip	NXP MCUX PWM16	`nxp,imx-pwm`
	on-chip	MCUX Timer/PWM Module (TPM)6	`nxp,kinetis-tpm`
SDHC	on-chip	NXP imx USDHC controller2	`nxp,imx-usdhc`
Sensors	on-chip	NXP TMPSNS1	`nxp,tmpsns`
Serial controller	on-chip	NXP LPUART1 11	`nxp,lpuart`
SPI	on-chip	NXP LPSPI controller6	`nxp,lpspi`
SPI	on-chip	NXP FlexSPI controller2	`nxp,imx-flexspi`
Timer	on-chip	ARMv7-M System Tick1	`arm,armv7m-systick`
USB	on-chip	NXP EHCI USB device mode2	`nxp,ehci`
USB	on-chip	NXP USB High Speed PHY2	`nxp,usbphy`
Watchdog	on-chip	NXP External Watchdog Monitor1	`nxp,ewm`
Watchdog	on-chip	NXP RT watchdog1 4	`nxp,rtwdog`

Connections and I/Os

The i.MX RT1186 SoC has multiple GPIO controllers. The following pins are used by the board for the default configuration:

Name	Function	Usage
GPIO_AON_08	LPUART1_TX	UART Console TX (CM33)
GPIO_AON_09	LPUART1_RX	UART Console RX (CM33)
GPIO_AD_13	LPUART3_TX	UART Console TX (CM7)
GPIO_AD_14	LPUART3_RX	UART Console RX (CM7)
GPIO2_IO09	GPIO	Red LED
GPIO2_IO11	GPIO	Green LED
GPIO3_IO07	GPIO	Blue LED
GPIO4_IO12	GPIO	User Button SW4

System Clock

The i.MX RT1186 SoC is configured to use SysTick as the system clock source. The Cortex-M33 core can run up to 300 MHz, and the Cortex-M7 core can run up to 800 MHz.

ITCM and DTCM

If placing zephyr,flash in ITCM or zephyr,sram in DTCM, the property zephyr,memory-region should be deleted from the memory device node. For example, this overlay moves the CM33 zephyr,sram to DTCM:

boards/nxp/frdm_imxrt1186/cm33_sram_dtcm.overlay

Serial Port

The i.MX RT1186 SoC has 8 LPUART peripherals. LPUART1/3 is configured for the console and is available on the Debug USB connector.

Programming and Debugging

The frdm_imxrt1186 board supports the runners and associated west commands listed below.

	flash	debug	debugserver	attach	rtt	reset
jlink	✅	✅	✅	✅	✅	✅
linkserver	✅ (default)	✅ (default)	✅	✅

Build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

A debug probe is used for both flashing and debugging the board. This board is configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.

When debugging the CM33 core, ensure jumper J60 is set to 1:OFF 2:OFF 3:ON.

When debugging the CM7 core, ensure jumper J60 is set to 1:ON 2:OFF 3:OFF.

Using LinkServer

LinkServer is the default debug host tool for this board and requires no additional configuration.

Using J-Link

Install the J-Link Debug Host Tools and make sure they are in your search path.

There are two options:

Short J40 and update the onboard MCU-Link debug circuit with Segger J-Link firmware.
Short J58 and use an J-Link External Debug Probe connected to J54 (note: J54 is not populated by default on the board).

Configuring a Console

Connect a USB Type-C cable from your PC to J23, and use the serial terminal of your choice(minicom, putty, etc.) with the following settings:

Speed: 115200
Data: 8 bits
Parity: None
Stop bits: 1

Flashing

Here is an example for the Hello World application for the CM33 core.

# From the root of the zephyr repository
west build -b frdm_imxrt1186/mimxrt1186/cm33 samples/hello_world
west flash

Open a serial terminal, reset the board (press the RESET button SW2), and you should see the following message in the terminal: (Note: When using LPUART3 as serial port, jumper J34 must be removed)

*** Booting Zephyr OS build v4.x.x ***
Hello World! frdm_imxrt1186/mimxrt1186/cm33

Note: By default, the CM33 core is the bootable core. The CM7 core cannot be directly: booted and must be started by the CM33 core.

Debugging

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b frdm_imxrt1186/mimxrt1186/cm33 samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

*** Booting Zephyr OS build v4.x.x ***
Hello World! frdm_imxrt1186/mimxrt1186/cm33

Support Resources for Zephyr

NXP Board Support Status
NXP Zephyr Downstream Software Development Kit
MCUXpresso for VS Code documentation, and Zephyr lab guides
NXP Zephyr Knowledge Hub
NXP’s Zephyr landing page (including training resources)
NXP Support Community forum for Zephyr

FRDM-iMXRT1186

FRDM-iMXRT1186

Overview

Hardware

Supported Features

frdm_imxrt1186/mimxrt1186/cm33 target

frdm_imxrt1186/mimxrt1186/cm7 target

Connections and I/Os

System Clock

ITCM and DTCM

Serial Port

Programming and Debugging

Configuring a Debug Probe

Using LinkServer

Using J-Link

Configuring a Console

Flashing

Debugging

Support Resources for Zephyr

`frdm_imxrt1186/mimxrt1186/cm33` target

`frdm_imxrt1186/mimxrt1186/cm7` target