FRDM-MCXL255

Overview

FRDM-MCXL255 is compact and scalable development board for rapid prototyping of MCX L25x MCUs. It offers industry standard headers for easy access to the MCUs I/Os, integrated open-standard serial interfaces, external flash memory and an on-board MCU-Link debugger. MCX L Series features Adaptive Dynamic Voltage Control (ADVC) for optimized power consumption at low frequency operation. Compared to traditional low-power MCUs, a dedicated ultra-low-power (ULP) Sense Domain allows operation of low-power peripherals while keeping the main core in Deep Power Mode. This avoids event triggering and keeps data acquisition to extremely low power levels.

Hardware

NXP MCX L255 MCU
On-board MCU-Link debugger with CMSIS-DAP
Arduino Header, mikroBUS, Pmod, Sensor port

Main domain

96MHz Cortex-M33 (with FPU, MPU, SIMD, Trustzone with 8 SAU regions)
512KB on chip Flash dual-bank on chip Flash
128KB RAM
Timers: 3x 32b Timers, Micro Tick Timer, Windowed WDT, OS Event Timer
Interfaces: 2x LPUART, 2x LPI2C, 2x LPSPI
Security Blocks: PKC Engine, RNG, SHA512, AES-256, Protected Flash Region, 2x Code Watchdog
Analog: 16b ADC, Analog Comparator

Always-on Domain

10MHz Cortex-M0+
32KB RAM
Interfaces: 1x LPUART, 1x LPI2C
Analog: 16b ADC, Analog Comparator, Temperature Sensor
Timers: RTC, LP Timers
Segment LCD, Keypad

For more information about the MCX-L255 SoC and FRDM-MCXL255 board, see:

Supported Features

The frdm_mcxl255 board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`frdm_mcxl255/mcxl255/cpu0` target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33F CPU1	`arm,cortex-m33f`
Clock control	on-chip	LPC SYSCON & CLKCTL IP node1	`nxp,lpc-syscon`
Clock control	on-chip	Generic fixed-rate clock provider4 1	`fixed-clock`
DMA	on-chip	NXP MCUX EDMA controller1 1	`nxp,mcux-edma`
Flash controller	on-chip	NXP MSF1 Flash Memory Module (FMU)1	`nxp,msf1`
GPIO & Headers	on-chip	Kinetis GPIO3 1	`nxp,kinetis-gpio`
Hardware information	on-chip	NXP LPC 128-bit Unique identifier1	`nxp,lpc-uid`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v8m-nvic`
Interrupt controller	on-chip	NXP Wakeup Unit (WUU)1	`nxp,wuu`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
Mailbox	on-chip	NXP i.MX Message Unit as Zephyr MBOX1	`nxp,mbox-imx-mu`
MMU / MPU	on-chip	ARMv8-M MPU (Memory Protection Unit)1	`arm,armv8m-mpu`
MTD	on-chip	Flash node1	`soc-nv-flash`
Pin control	on-chip	NXP PORT Pin Controller4	`nxp,port-pinmux`
Pin control	on-chip	NXP PORT Pin Controller1	`nxp,port-pinctrl`
Power management	on-chip	NXP Core Mode Controller (CMC)1	`nxp,cmc`
Reset controller	on-chip	LPC SYSCON Peripheral reset controller1	`nxp,lpc-syscon-reset`
Serial controller	on-chip	NXP LPUART1 2	`nxp,lpuart`
SRAM	on-chip	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	ARMv8-M System Tick1	`arm,armv8m-systick`

Targets available

The default configuration enables the first core only. CPU0 is the only target that can run standalone. CPU1 is not supported.

Connections and IOs

The MCX-L255 SoC has 4 gpio controllers and has pinmux registers which can be used to configure the functionality of a pin.

Name	Function	Usage
P2_10	UART	UART RX cpu0
P2_11	UART	UART TX cpu0
P0_7	UART	UART RX cpu1
P0_6	UART	UART TX cpu1

System Clock

The MCX-L255 SoC is configured to use FRO 96M (FIRC) running at 96MHz as a source for the system clock.

Serial Port

The FRDM-MCXL255 SoC has 3 LPUART interfaces. The default console is LPUART0.

Programming and Debugging

The frdm_mcxl255 board supports the runners and associated west commands listed below.

	flash	debug	debugserver	attach	rtt	reset
jlink	✅	✅	✅	✅	✅	✅
linkserver	✅ (default)	✅ (default)	✅	✅

Build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

A debug probe is used for both flashing and debugging the board. This board is configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.

Using LinkServer

Linkserver is the default runner for this board, and supports the factory default MCU-Link firmware. Follow the instructions in MCU-Link CMSIS-DAP Onboard Debug Probe to reprogram the default MCU-Link firmware. This only needs to be done if the default onboard debug circuit firmware was changed. To put the board in ISP mode to program the firmware, short jumper keep SW3 pressed during power-up or reset, then release it.

Using J-Link

There are two options. The onboard debug circuit can be updated with Segger J-Link firmware by following the instructions in MCU-Link JLink Onboard Debug Probe. To be able to program the firmware, you need to put the board in ISP mode by keeping SW3 pressed during power-up or reset, then release it.

The second option is to attach a J-Link External Debug Probe to the 10-pin SWD connector (J17) of the board. For both options use the -r jlink option with west to use the jlink runner.

west flash -r jlink

Configuring a Console

Connect a USB cable from your PC to J16, and use the serial terminal of your choice (minicom, putty, etc.) with the following settings:

Speed: 115200
Data: 8 bits
Parity: None
Stop bits: 1

Flashing

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b frdm_mcxl255/mcxl255/cpu0 samples/hello_world
west flash

Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:

*** Booting Zephyr OS build v4.3.0-2208-gcf34f44c1e18 ***
Hello World! frdm_mcxl255/mcxl255/cpu0

Debugging