FRDM-IMXRT700
Overview
The FRDM-IMXRT700 is a compact, low-cost development board based on the NXP i.MX RT700 crossover MCU. The i.MX RT700 is a multicore device composed of a high-performance main-compute subsystem and a secondary “always-on” sense-compute subsystem, together with specialized coprocessors.
The main-compute subsystem has a primary Arm® Cortex®-M33 (CPU0) and an integrated Cadence® Tensilica® HiFi 4 DSP.
The sense-compute subsystem has a second Arm® Cortex®-M33 (CPU1) and an integrated Cadence® Tensilica® HiFi 1 DSP.
This Zephyr board port currently provides baseline support for the two
Cortex-M33 cores (cm33_cpu0 and cm33_cpu1).
Hardware
MIMXRT798S SoC:
Arm Cortex-M33 (CPU0) main-compute core
Arm Cortex-M33 (CPU1) sense-compute core
HiFi 4 and HiFi 1 DSP cores (not supported by this port)
On-board MCU-Link debug probe with UART, SWD and SPI/I2C bridging
Quad SPI flash for code storage (XSPI0)
RGB user LED and user buttons
Arduino-compatible and MikroBUS expansion headers
For more information about the i.MX RT700 SoC, see the i.MX RT700 Website [1].
Supported Features
The frdm_imxrt700 board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
frdm_imxrt700/mimxrt798s/cm33_cpu0 target
On-target memory for this board target: 512 KiB of RAM, 32 MiB of Flash.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M33F CPU1 |
|
ADC |
on-chip |
LPC LPADC1 |
|
Audio |
on-chip |
NXP PDM Microphone Interface (MICFIL)1 |
|
Clock control |
on-chip |
LPC SYSCON & CLKCTL IP node8 |
|
clock-monitor |
on-chip |
NXP Frequency Measurement (FREQME) module1 |
|
Comparator |
on-chip |
NXP Kinetis ACMP (Analog CoMParator)1 |
|
Counter |
on-chip |
NXP IRTC wake timer exposed through the counter API1 |
|
on-chip |
NXP MCUX Standard Timer/Counter5 |
||
on-chip |
NXP Multirate Timer1 |
||
on-chip |
NXP Multirate Timer Channel4 |
||
CRC |
on-chip |
NXP CRC device1 |
|
DMA |
on-chip |
NXP MCUX EDMA controller2 |
|
Flash controller |
on-board |
NXP XSPI Flash Controller1 |
|
GPIO & Headers |
on-chip |
||
Hardware information |
on-chip |
NXP RSTCTL get reset cause flags1 |
|
on-chip |
NXP LPC 128-bit Unique identifier1 |
||
Hardware spinlock |
on-chip |
NXP SEMA42 hardware semaphore controller2 |
|
I2C |
on-chip |
NXP LPI2C controller15 |
|
I2S |
on-chip |
NXP mcux SAI-I2S controller3 |
|
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv8-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
Mailbox |
on-chip |
NXP i.MX Message Unit as Zephyr MBOX3 |
|
Multi-Function Device |
on-chip |
||
MIPI-DBI |
on-chip |
DBI settings for NXP DCnano LCD controller1 |
|
MIPI-DSI |
on-chip |
NXP MCUX MIPI DSI 2L1 |
|
Miscellaneous |
on-chip |
NXP FlexIO controller1 |
|
on-chip |
NXP i.MX RTxxx DSP control driver (i.MX RT700 HiFi 4 DSP)1 |
||
MMU / MPU |
on-chip |
ARMv8-M MPU (Memory Protection Unit)1 |
|
MTD |
on-board |
Flash node1 |
|
mux |
on-chip |
NXP INPUTMUX peripheral binding1 |
|
NVMEM |
on-chip |
Fixed layout for Non-Volatile memory1 |
|
OTP memory |
on-chip |
NXP RT7xx OCOTP1 |
|
Pin control |
on-chip |
LPC I/O Pin Configuration (IOCON)3 |
|
on-chip |
RT600/RT500 Pin Controller1 |
||
PWM |
on-chip |
NXP SCTimer PWM1 |
|
Reset controller |
on-chip |
NXP RSTCTL Peripheral reset controller4 |
|
RTC |
on-chip |
IRTC1 |
|
SDHC |
on-chip |
NXP imx USDHC controller2 |
|
Sensors |
on-chip |
NXP PMC temperature sensor (PMC-TMPSNS)1 |
|
Serial controller |
on-chip |
||
SPI |
on-chip |
NXP LPSPI controller16 |
|
SRAM |
on-chip |
Generic on-chip SRAM7 |
|
Timer |
on-chip |
ARMv8-M System Tick1 |
|
on-chip |
NXP OS Timer on i.MX-RT5xx/6xx1 |
||
USB |
on-chip |
NXP EHCI USB device mode2 |
|
on-chip |
NXP EHCI USB host controller2 |
||
on-chip |
NXP USB High Speed PHY1 |
||
Watchdog |
on-chip |
LPC Windowed Watchdog Timer2 |
|
Wakeup Controller |
on-chip |
NXP SLEEPCON (Sleep Controller) acting as a Wakeup Controller (WUC)1 |
|
xSPI |
on-chip |
frdm_imxrt700/mimxrt798s/cm33_cpu1 target
On-target memory for this board target: 256 KiB of RAM, 512 KiB of Flash.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M33F CPU1 |
|
ADC |
on-chip |
LPC LPADC1 |
|
Clock control |
on-chip |
LPC SYSCON & CLKCTL IP node8 |
|
Comparator |
on-chip |
NXP Kinetis ACMP (Analog CoMParator)1 |
|
Counter |
on-chip |
NXP MCUX Standard Timer/Counter3 |
|
GPIO & Headers |
on-chip |
||
Hardware information |
on-chip |
NXP RSTCTL get reset cause flags1 |
|
Hardware spinlock |
on-chip |
NXP SEMA42 hardware semaphore controller2 |
|
I2C |
on-chip |
NXP LPI2C controller5 |
|
I3C |
on-chip |
NXP MCUX I3C controller2 |
|
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv8-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
Mailbox |
on-chip |
NXP i.MX Message Unit as Zephyr MBOX3 |
|
Multi-Function Device |
on-chip |
||
MMU / MPU |
on-chip |
ARMv8-M MPU (Memory Protection Unit)1 |
|
Pin control |
on-chip |
LPC I/O Pin Configuration (IOCON)2 |
|
on-chip |
RT600/RT500 Pin Controller1 |
||
Reset controller |
on-chip |
NXP RSTCTL Peripheral reset controller4 |
|
RTC |
on-chip |
IRTC1 |
|
Serial controller |
on-chip |
||
SPI |
on-chip |
NXP LPSPI controller4 |
|
SRAM |
on-chip |
Generic on-chip SRAM7 |
|
Timer |
on-chip |
ARMv8-M System Tick1 |
|
on-chip |
NXP OS Timer on i.MX-RT5xx/6xx1 |
||
Wakeup Controller |
on-chip |
NXP SLEEPCON (Sleep Controller) acting as a Wakeup Controller (WUC)1 |
|
xSPI |
on-chip |
NXP XSPI controller1 |
The frdm_imxrt700 board targets enable the following features in this
baseline port:
Interface |
Controller |
Driver/Component |
|---|---|---|
GPIO |
on-chip |
gpio |
UART |
on-chip |
serial port (debug console) |
Additional peripherals will be enabled in follow-up work.
Programming and Debugging
The frdm_imxrt700 board supports the runners and associated west commands listed below.
| flash | debug | debugserver | rtt | reset | attach | |
|---|---|---|---|---|---|---|
| jlink | ✅ (default) | ✅ (default) | ✅ | ✅ | ✅ | ✅ |
This board is flashed and debugged using a J-Link debug probe, for example the on-board MCU-Link programmed with J-Link firmware, or an external J-Link.
Note
LinkServer is not supported yet. The current LinkServer release has no FRDM-IMXRT700 board definition and ships only an octal flashloader for the i.MX RT700 XSPI, so it cannot program the board’s on-board quad SPI NOR flash. Once a LinkServer release adds FRDM-IMXRT700 support, the supported version will be recorded here and the LinkServer flashing/debugging steps added.
Building
The debug console of CPU0 is routed to FLEXCOMM0 (LPUART0) through the MCU-Link bridge. CPU1 uses FLEXCOMM19 (LPUART19).
Build and the Hello World sample for CPU0:
# From the root of the zephyr repository
west build -b frdm_imxrt700/mimxrt798s/cm33_cpu0 samples/hello_world
west flash
Build the Blinky sample for CPU0:
# From the root of the zephyr repository
west build -b frdm_imxrt700/mimxrt798s/cm33_cpu0 samples/basic/blinky
west flash
To target the sense-compute core (CPU1), use the
frdm_imxrt700/mimxrt798s/cm33_cpu1 board target.