MR-MCXN-T1
Overview
The NXP MR-MCXN-T1 is a dual-core mobile-robotics controller built around the NXP MCXN947 MCU. The MCXN947 pairs two Arm Cortex-M33 cores running at up to 150 MHz. The cores operate asymmetrically (AMP) and SMP is not supported. On this board CPU0 runs a TrustZone-secure image and CPU1 acts as a secondary core.
The board provides 100BASE-T1 single-pair Ethernet, dual CAN, an on-board inertial measurement unit, and a stacking header that mates a series of expansion boards (optical flow, GNSS and flex IO).
Hardware
MCXN947 MCU
Dual Cortex-M33 at up to 150 MHz (AMP, each core runs its own image)
2 MB flash
512 KB SRAM
Ethernet
Synopsys DesignWare Ethernet MAC 10/100/1G Quality-of-Service controller (NXP ENET QoS) with 100BASE-T1 single-pair Ethernet through a TJA1103 PHY and IEEE 1588 hardware timestamping
CAN
Two FlexCAN controllers, each behind a TJA1462 CAN transceiver
Sensors
ICM-45686 6-axis IMU (hub)
BMP581 barometer (I3C)
BMM350 magnetometer (I3C)
Indicator
APA102 addressable LED driven over FlexIO
Expansion
Stacking header exposing SPI, I2C, UART, PWM and ADC buses plus GPIO control lines
Supported Features
The mr_mcxn_t1 board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
mr_mcxn_t1/mcxn947/cpu0 target
On-target memory for this board target: 320 KiB of RAM, 2 MiB of Flash.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M33F CPU1 |
|
ADC |
on-chip |
LPC LPADC2 |
|
Audio |
on-chip |
NXP PDM Microphone Interface (MICFIL)1 |
|
CAN |
on-chip |
NXP FlexCAN CANFD controller2 |
|
Clock control |
on-chip |
LPC SYSCON & CLKCTL IP node1 |
|
Clock monitor |
on-chip |
NXP Frequency Measurement (FREQME) module1 |
|
Comparator |
on-chip |
NXP Low Power Comparator (LPCMP)3 |
|
Counter |
on-chip |
||
on-chip |
NXP LPTMR2 |
||
on-chip |
NXP Multirate Timer1 |
||
on-chip |
NXP Multirate Timer Channel4 |
||
CRC |
on-chip |
NXP CRC device1 |
|
Cryptographic accelerator |
on-chip |
NXP EdgeLock Secure Subsystem1 |
|
DAC |
on-chip |
NXP MCUX LPDAC2 |
|
on-chip |
NXP MCUX HPDAC (14-bit DAC)1 |
||
DMA |
on-chip |
||
on-chip |
NXP SmartDMA controller1 |
||
DSP |
on-chip |
NXP PowerQuad DSP coprocessor1 |
|
EDAC |
on-chip |
NXP Error Injection Module1 |
|
on-chip |
NXP Error Reporting Module1 |
||
Ethernet |
on-chip |
NXP ENET QOS Ethernet Controller1 |
|
on-chip |
Synopsys DesignWare MAC PTP (Precision Time Protocol) Clock1 |
||
on-chip |
Synopsys DesignWare MAC MDIO controller1 |
||
on-board |
TJA1103 PHY1 |
||
Flash controller |
on-chip |
NXP MSF1 Flash Memory Module (FMU)1 |
|
GPIO & Headers |
on-chip |
||
on-board |
GPIO control lines exposed on the MR-MCXN-T1 stacking header1 |
||
Hardware information |
on-chip |
NXP LPC 128-bit Unique identifier1 |
|
Hardware spinlock |
on-chip |
NXP SEMA42 hardware semaphore controller1 |
|
I2C |
on-chip |
NXP LPI2C controller10 |
|
I2S |
on-chip |
NXP mcux SAI-I2S controller2 |
|
I3C |
on-chip |
NXP MCUX I3C controller2 |
|
Input |
on-chip |
NXP TSI V6 Touch Sensing Input Device1 |
|
Interrupt controller |
on-chip |
ARMv8-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED strip |
on-board |
APA102 SPI LED strip1 |
|
Mailbox |
on-chip |
NXP Mailbox Unit as Zephyr MBOX1 |
|
Multi-Function Device |
on-chip |
||
MIPI-DBI |
on-chip |
NXP FlexIO LCD controller1 |
|
Miscellaneous |
on-chip |
NXP FlexIO controller1 |
|
MMU / MPU |
on-chip |
ARMv8-M MPU (Memory Protection Unit)1 |
|
MTD |
on-chip |
Flash node1 |
|
MUX |
on-chip |
NXP INPUTMUX peripheral binding1 |
|
OPAMP |
on-chip |
NXP Operational Amplifier (opamp)3 |
|
OTP memory |
on-chip |
NXP OTPC eFuse controller1 |
|
PHY |
on-board |
Simple GPIO controlled CAN transceiver2 |
|
Pin control |
on-chip |
NXP PORT Pin Controller6 |
|
on-chip |
NXP PORT Pin Controller1 |
||
Power management |
on-chip |
NXP System Power Control (SPC)1 |
|
on-chip |
NXP Core Mode Controller (CMC)1 |
||
on-chip |
NXP Smart Power Switch (VBAT)1 |
||
Power domain |
on-chip |
This power domain will Turn On and Off devices when transitioning in and out a specified Power State1 |
|
PWM |
on-chip |
NXP eFLEX PWM module with mcux-pwm submodules2 |
|
on-chip |
NXP MCUX PWM8 |
||
on-chip |
NXP SCTimer PWM1 |
||
Regulator |
on-chip |
NXP VREF SOC peripheral1 |
|
Reset controller |
on-chip |
LPC SYSCON Peripheral reset controller1 |
|
RNG |
on-chip |
NXP EdgeLock Secure Subsystem TRNG1 |
|
RTC |
on-chip |
IRTC1 |
|
SDHC |
on-chip |
NXP imx USDHC controller1 |
|
Sensors |
on-board |
ICM45686 High-precision 6-axis motion tracking device When setting the accel-pm, accel-range, accel-odr, gyro-pm, gyro-range, gyro-odr properties in a .dts or .dtsi file you may include icm45686.h and use the macros defined there1 |
|
on-chip |
NXP MCUX QDC2 |
||
on-board |
The BMP581 is a Barometric pressure sensor on I3C1 |
||
on-board |
Bosch BMM350 Geomagnetic sensor on I3C1 |
||
Serial controller |
on-chip |
||
SPI |
on-chip |
||
on-board |
NXP FlexIO SPI controller1 |
||
on-chip |
NXP FlexSPI controller1 |
||
SRAM |
on-chip |
Generic on-chip SRAM3 |
|
Timer |
on-chip |
ARMv8-M System Tick1 |
|
on-chip |
NXP OS Timer on i.MX-RT5xx/6xx1 |
||
USB |
on-chip |
NPX Kinetis USBFSOTG Controller in device mode1 |
|
on-chip |
NXP EHCI USB device mode1 |
||
on-chip |
NXP USB High Speed PHY1 |
||
Watchdog |
on-chip |
LPC Windowed Watchdog Timer1 |
|
on-chip |
NXP External Watchdog Monitor1 |
||
Wakeup Controller |
on-chip |
NXP Wakeup Unit (WUU) acting as a Wakeup Controller (WUC)1 |
mr_mcxn_t1/mcxn947/cpu1 target
On-target memory for this board target: 64 KiB of RAM, 2 MiB of Flash.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M33 CPU1 |
|
ADC |
on-chip |
LPC LPADC2 |
|
Audio |
on-chip |
NXP PDM Microphone Interface (MICFIL)1 |
|
CAN |
on-chip |
NXP FlexCAN CANFD controller2 |
|
Clock control |
on-chip |
LPC SYSCON & CLKCTL IP node1 |
|
Clock monitor |
on-chip |
NXP Frequency Measurement (FREQME) module1 |
|
Comparator |
on-chip |
NXP Low Power Comparator (LPCMP)3 |
|
Counter |
on-chip |
NXP MCUX Standard Timer/Counter5 |
|
on-chip |
NXP LPTMR2 |
||
on-chip |
NXP Multirate Timer1 |
||
on-chip |
NXP Multirate Timer Channel4 |
||
CRC |
on-chip |
NXP CRC device1 |
|
Cryptographic accelerator |
on-chip |
NXP EdgeLock Secure Subsystem1 |
|
DAC |
on-chip |
NXP MCUX LPDAC2 |
|
on-chip |
NXP MCUX HPDAC (14-bit DAC)1 |
||
DMA |
on-chip |
||
on-chip |
NXP SmartDMA controller1 |
||
DSP |
on-chip |
NXP PowerQuad DSP coprocessor1 |
|
EDAC |
on-chip |
NXP Error Injection Module1 |
|
on-chip |
NXP Error Reporting Module1 |
||
Ethernet |
on-chip |
NXP ENET QOS Ethernet Controller1 |
|
on-chip |
Synopsys DesignWare MAC PTP (Precision Time Protocol) Clock1 |
||
on-chip |
Synopsys DesignWare MAC MDIO controller1 |
||
on-board |
TJA1103 PHY1 |
||
Flash controller |
on-chip |
NXP MSF1 Flash Memory Module (FMU)1 |
|
GPIO & Headers |
on-chip |
Kinetis GPIO6 |
|
on-board |
GPIO control lines exposed on the MR-MCXN-T1 stacking header1 |
||
Hardware information |
on-chip |
NXP LPC 128-bit Unique identifier1 |
|
Hardware spinlock |
on-chip |
NXP SEMA42 hardware semaphore controller1 |
|
I2C |
on-chip |
NXP LPI2C controller10 |
|
I2S |
on-chip |
NXP mcux SAI-I2S controller2 |
|
I3C |
on-chip |
NXP MCUX I3C controller2 |
|
Input |
on-chip |
NXP TSI V6 Touch Sensing Input Device1 |
|
Interrupt controller |
on-chip |
ARMv8-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED strip |
on-board |
APA102 SPI LED strip1 |
|
Mailbox |
on-chip |
NXP Mailbox Unit as Zephyr MBOX1 |
|
Multi-Function Device |
on-chip |
Low Power Flexcomm10 |
|
MIPI-DBI |
on-chip |
NXP FlexIO LCD controller1 |
|
Miscellaneous |
on-chip |
NXP FlexIO controller1 |
|
MTD |
on-chip |
Flash node1 |
|
MUX |
on-chip |
NXP INPUTMUX peripheral binding1 |
|
OPAMP |
on-chip |
NXP Operational Amplifier (opamp)3 |
|
OTP memory |
on-chip |
NXP OTPC eFuse controller1 |
|
PHY |
on-board |
Simple GPIO controlled CAN transceiver2 |
|
Pin control |
on-chip |
NXP PORT Pin Controller6 |
|
on-chip |
NXP PORT Pin Controller1 |
||
Power management |
on-chip |
NXP System Power Control (SPC)1 |
|
on-chip |
NXP Core Mode Controller (CMC)1 |
||
on-chip |
NXP Smart Power Switch (VBAT)1 |
||
Power domain |
on-chip |
This power domain will Turn On and Off devices when transitioning in and out a specified Power State1 |
|
PWM |
on-chip |
NXP eFLEX PWM module with mcux-pwm submodules2 |
|
on-chip |
NXP MCUX PWM8 |
||
on-chip |
NXP SCTimer PWM1 |
||
Regulator |
on-chip |
NXP VREF SOC peripheral1 |
|
Reset controller |
on-chip |
LPC SYSCON Peripheral reset controller1 |
|
RNG |
on-chip |
NXP EdgeLock Secure Subsystem TRNG1 |
|
RTC |
on-chip |
IRTC1 |
|
SDHC |
on-chip |
NXP imx USDHC controller1 |
|
Sensors |
on-board |
ICM45686 High-precision 6-axis motion tracking device When setting the accel-pm, accel-range, accel-odr, gyro-pm, gyro-range, gyro-odr properties in a .dts or .dtsi file you may include icm45686.h and use the macros defined there1 |
|
on-chip |
NXP MCUX QDC2 |
||
on-board |
The BMP581 is a Barometric pressure sensor on I3C1 |
||
on-board |
Bosch BMM350 Geomagnetic sensor on I3C1 |
||
Serial controller |
on-chip |
NXP LPUART10 |
|
SPI |
on-chip |
NXP LPSPI controller10 |
|
on-board |
NXP FlexIO SPI controller1 |
||
on-chip |
NXP FlexSPI controller1 |
||
SRAM |
on-chip |
Generic on-chip SRAM3 |
|
Timer |
on-chip |
ARMv8-M System Tick1 |
|
on-chip |
NXP OS Timer on i.MX-RT5xx/6xx1 |
||
USB |
on-chip |
NPX Kinetis USBFSOTG Controller in device mode1 |
|
on-chip |
NXP EHCI USB device mode1 |
||
on-chip |
NXP USB High Speed PHY1 |
||
Watchdog |
on-chip |
LPC Windowed Watchdog Timer1 |
|
on-chip |
NXP External Watchdog Monitor1 |
||
Wakeup Controller |
on-chip |
NXP Wakeup Unit (WUU) acting as a Wakeup Controller (WUC)1 |
Connections and IOs
The stacking header is described in the devicetree by the
mr_mcxn_t1_header GPIO nexus (compatible mr-mcxn-t1-header) and by
labeled bus nodes for each exposed peripheral. Expansion-board overlays
reference these nexus names rather than raw SoC controllers.
FlexCOMM3 and FlexCOMM7 are multiplexed across expansion boards, so only one function per instance (SPI, UART or I2C) can be active at a time.
I3C is disabled by default. The I3C bus stalls in a busy-wait at startup, and keeping it off frees flexcomm1 for the physical LPUART1 console. Re-enable the bus and its two sensors once the startup behavior is resolved.
Programming and Debugging
The mr_mcxn_t1 board supports the runners and associated west commands listed below.
| flash | debug | attach | debugserver | rtt | reset | |
|---|---|---|---|---|---|---|
| jlink | ✅ (default) | ✅ (default) | ✅ | ✅ | ✅ | ✅ |
| linkserver | ✅ | ✅ | ✅ | ✅ | ||
| pyocd | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
The board is programmed and debugged with the on-board or an external SWD
probe. Build and flash the hello_world sample for CPU0 with:
# From the root of the zephyr repository
west build -b mr_mcxn_t1/mcxn947/cpu0 samples/hello_world
west flash
Open a serial terminal at 115200 8N1 on the LPUART1 console to see the output.
References
FRDM-MCXN947 for the MCXN947 SoC reference board