MIMXRT2660-EVK

Board Overview

Name:

mimxrt2660_evk

Vendor:

NXP Semiconductors

Status:

Maintained

Architecture:

arm

SoC:

mimxrt2663

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MIMXRT2660-EVK

Overview

The MIMXRT2660-EVK is an evaluation board for the NXP i.MX RT266x family, built around the MIMXRT2663 crossover MCU. The i.MX RT266x is a subsystem-partitioned design: a single Arm Cortex-M85 compute core sits alongside HSP, MAIN, WAKE, AUDIO, MEDIA, COMM, SYSCON and VBAT domains, each with its own clock and power controls.

Hardware

• MIMXRT2663 crossover MCU:

  • Arm Cortex-M85 at up to 1 GHz, with Helium, TrustZone, MPU and L1 caches

  • 256 KB ITCM, 256 KB DTCM, and three 256 KB banks of on-chip RAM

  • Neutron N256 neural processing unit and a display/graphics subsystem

  • Two xSPI interfaces (one 8-bit, one 16-bit), 8 UART, 4 I2C, 2 I3C, 6 SPI

  • Two Gbps Ethernet with TSN, two 10BASE-T1S, three CAN-FD

  • Security enclave (EdgeLock) and a last-level cache

• Board:

  • MIMXRT2663CVVAA, Industrial grade, 289BGA 0.8 mm, 1 GHz

  • 64 MB Winbond W25H512NWEAM serial NOR flash on XSPI0

  • 32 MB Winbond W958D6NMYA Xccela PSRAM on XSPI1

  • eMMC, SD card slot, Ethernet, USB

  • On-board MCU-Link debug probe

For more information about the i.MX RT266x SoC and this board, see the i.MX RT2660 Reference Manual [1] and the i.MX RT2660 Data Sheet [1].

Memory Layout

This board executes in place from external flash and uses external RAM:

• zephyr,flash is the 64 MB XSPI0 NOR flash; code runs in place from it.

• zephyr,sram is the 32 MB XSPI1 PSRAM; .data, .bss and the kernel stacks and heap live there.

• ITCM holds the clock bring-up window code, and a scratch stack in the DTCM carries the window itself: reprogramming the PLLs requires parking both XSPI controllers, so for as long as the window is open neither the code nor the stack it runs on may be in external memory. Nothing else has to move, so an application keeps the full PSRAM for its own stacks and heap and the TCMs stay free for it to use.

The boot ROM initializes both memories from the boot header before this image runs – the flash configuration block for the NOR and the external memory configuration data for the PSRAM.

Note

This SoC’s boot ROM uses a container-based (AHAB) image format and does not read an image vector table. The build emits all three blocks the ROM reads – the flash configuration block at offset 0x400, the external-memory configuration data at 0xA00 and the AHAB container at 0x1000 – and places the image itself at 0xC000, so zephyr.bin written to the boot flash runs from a cold reset with no post-build step. Signing is not required on an evaluation board: the out-of-fab life cycle ignores authentication errors, so the container carries an empty signature block.

Note

The flash is used for execution only: this target carries no flash driver and no partitions, so the flash API, MCUboot and settings-on-flash are not available. Enabling the flash driver requires portability work in Zephyr’s shared XSPI drivers, which use xspi_config_t fields this SoC does not implement.

Supported Features

The mimxrt2660_evk board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

mimxrt2660_evk/mimxrt2663/cm85 target

On-target memory for this board target: 32 MiB of RAM, 64 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M85 CPU1	arm,cortex-m85
ADC	on-chip	LPC LPADC2	nxp,lpc-lpadc
CAN	on-chip	NXP FlexCAN CANFD controller3	nxp,flexcan-fd
Clock control	on-chip	NXP i.MX CGU analog block (CGUANA) – the block that generates clocks1	nxp,imx-cguana
	on-chip	Crystal oscillator in an NXP i.MX CGU analog block (CGUANA)1	nxp,imx-cguana-sxosc
	on-chip	High-frequency free-running oscillator in an NXP i.MX CGU analog block1	nxp,imx-cguana-fro192m
	on-chip	Low-frequency free-running oscillator in an NXP i.MX CGU analog block1	nxp,imx-cguana-fro12m
	on-chip	Integer PLL in an NXP i.MX CGU analog block1	nxp,imx-cguana-core-pll
	on-chip	Fractional PLL in an NXP i.MX CGU analog block2	nxp,imx-cguana-frac-pll
	on-chip	Audio/Video PLL in an NXP i.MX CGU analog block2	nxp,imx-cguana-avpll
	on-chip	NXP i.MX Clock Controller Module, rev37	nxp,imx-ccm-rev3
	on-chip	One configurable clock root of an NXP i.MX CCM rev3 controller20	nxp,imx-ccm-rev3-root
Comparator	on-chip	NXP Kinetis ACMP (Analog CoMParator)4	nxp,kinetis-acmp
Counter	on-chip	NXP MCUX Quad Timer (QTMR)4	nxp,imx-qtmr
	on-chip	NXP MCUX Quad Timer Channel16	nxp,imx-tmr
	on-chip	NXP Low Power Periodic Interrupt Timer (LPIT)2	nxp,lpit
	on-chip	Child node for the Low Power Periodic Interrupt Timer node, intended for an individual timer channel8	nxp,lpit-channel
	on-chip	NXP LPTMR3	nxp,lptmr
CRC	on-chip	NXP CRC device1	nxp,crc
DAC	on-chip	NXP MCUX LPDAC1	nxp,lpdac
DMA	on-chip	NXP MCUX EDMA controller4	nxp,mcux-edma
Ethernet	on-chip	NXP ENET IP Module1	nxp,enet
	on-chip	NXP ENET MAC/L2 Device1	nxp,enet-mac
	on-chip	NXP ENET MDIO Features1	nxp,enet-mdio
	on-chip	NXP ENET PTP (Precision Time Protocol) Clock1	nxp,enet-ptp-clock
	on-chip	NXP ENET QOS Ethernet Controller1	nxp,enet-qos
	on-chip	Synopsys DesignWare MAC1	snps,dwmac
Flash controller	on-board	NXP XSPI Flash Controller1	nxp,xspi-nor
GPIO & Headers	on-chip	NXP i.MX GPIO controller25	nxp,imx-gpio-v2
I2C	on-chip	NXP LPI2C controller4	nxp,lpi2c
I2S	on-chip	NXP mcux SAI-I2S controller3	nxp,mcux-i2s
I3C	on-chip	NXP MCUX I3C controller2	nxp,mcux-i3c
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)1	arm,v8.1m-nvic
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
Miscellaneous	on-chip	NXP FlexIO controller3	nxp,flexio
MMU / MPU	on-chip	ARMv8-M MPU (Memory Protection Unit)1	arm,armv8m-mpu
MTD	on-board	Flash node1	soc-nv-flash
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node3	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in an MCUX RT266x SoC’s devicetree3	nxp,mcux-rt266x-pinctrl
PWM	on-chip	NXP eFLEX PWM module with mcux-pwm submodules4	nxp,flexpwm
	on-chip	NXP MCUX PWM16	nxp,imx-pwm
	on-chip	MCUX Timer/PWM Module (TPM)8	nxp,kinetis-tpm
SDHC	on-chip	NXP imx USDHC controller2	nxp,imx-usdhc
Sensors	on-chip	NXP MCUX QDEC4	nxp,mcux-qdec
Serial controller	on-chip	NXP LPUART17	nxp,lpuart
SPI	on-chip	NXP LPSPI controller6	nxp,lpspi
Timer	on-chip	ARMv8.1-M System Tick1	arm,armv8.1m-systick
USB	on-chip	NXP EHCI USB device mode1	nxp,ehci
	on-chip	NXP USB High Speed PHY1	nxp,usbphy
Video	on-chip	NXP MCUX CMOS sensor interface1	nxp,imx-csi
Watchdog	on-chip	NXP External Watchdog Monitor1	nxp,ewm
xSPI	on-chip	NXP XSPI controller11	nxp,xspi

Connections and I/Os

Function	Signal	Pad
Console	LPUART0 TXD	PIO3_30
Console	LPUART0 RXD	PIO3_31
User LED	HSP GPIO0 26	PIO2_26 (D16, active low)
User SW	WAKE GPIO0 0	PIO1_0 (WAKE_SS_BTN)
XSPI0	SCLK0, SS0_N, DATA0..DATA3	PIO6_0, PIO6_1, PIO6_2..PIO6_5 (quad; the flash is not wired octal on this board)

The debug console runs at 115200 8N1 on the MCU-Link virtual COM port.

System Clock

The board’s boot clock configuration enters the Over Drive Run operating point through the power controller, so the Cortex-M85 runs at 1 GHz. Because that transition also has to hand the PLL reference over from the on-chip oscillator to the board crystal, part of it executes from RAM with the caches off and both xSPI controllers disabled – which is why that code, and the stack it runs on, live in ITCM and DTCM rather than in either external memory.

The system timer counts an external 24 MHz reference derived from the board crystal (the compute subsystem’s SysTick clock root), not the core clock, so tick timing is crystal-accurate rather than dependent on the core frequency.

Peripheral clock roots are described in devicetree as nxp,imx-ccm-rev3-root nodes, and there are two ways to program them, matching where a root sits in the tree.

Upstream and shared roots – the CGU distribution roots and any root without a single consumer, such as main_rootclk or the peri3_rootclk root that feeds every PERI3-sourced peripheral – carry their mux and divider as properties on the root node itself. An application overlay can retarget one of these without editing board C code, which moves every leaf that draws from it at once. For example, to re-source the shared PERI3 root:

&peri3_rootclk {
        clock-mux = <IMX_CCM_MUX_PERI3_SYSPLL_DIVOUT2>;
        clock-div = <1>;
};

Leaf peripheral roots – the per-instance functional-clock roots owned by a single device, such as each LPUART – instead carry their default mux and divider inline on the consuming peripheral node, as a second clocks entry alongside the gate. This gives every such device a board default without a separate overlay. The console LPUART0 uses PERI3 divided by 5 (80 MHz):

&lpuart0 {
        clock-names = "gate", "source";
        clocks = <&ccm IMX_CCM_CLK(IMX_CCM_LPCG_MAIN_HSP_LPUART0,
                                   IMX_CCM_ROOT_MAIN_LPUART0_FCLK)>,
                 <&ccm IMX_CCM_ROOT_CFG(IMX_CCM_ROOT_MAIN_LPUART0_FCLK,
                                        IMX_CCM_MUX_LPUART0_PERI3, 5, 1)>;
};

Only the LPUART driver reads that second entry today. A peripheral whose driver does not yet apply it keeps its root at the reset value, so adding the entry alone changes nothing for LPSPI, LPI2C or the others.

Note

Only the leaf peripheral roots are safe to retarget this way. The analog sources, the CPU and bus roots and the PLL-distribution roots are devicetree nodes too – the SoC clock bring-up reads them rather than hardcoding values – but they are parked, powered down and re-hopped by the reference hand-over described above, so a property edit alone does not make a different setting work. The two xSPI functional roots are declared on xspi0/xspi1 instead of as controller children, and are additionally written by hand inside that window.

Programming and Debugging

The mimxrt2660_evk board supports the runners and associated west commands listed below.

	flash	debug	attach	debugserver	rtt	reset
jlink	✅	✅	✅	✅	✅	✅
linkserver	✅ (default)	✅ (default)	✅	✅

Build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

This board is configured by default to use the on-board MCU-Link CMSIS-DAP Onboard Debug Probe.

Using LinkServer

LinkServer is the default runner for this board. LinkServer v26.09 or newer is required; older versions do not include the MIMXRT2663 device. Install LinkServer Debug Host Tools and make sure they are in your search path, then build and flash with:

# From the root of the zephyr repository
west build -b mimxrt2660_evk/mimxrt2663/cm85 samples/hello_world
west flash

Using J-Link

The onboard debug circuit can be updated with Segger J-Link firmware by following the instructions in MCU-Link JLink Onboard Debug Probe, or attach an external J-Link External Debug Probe to the SWD header.

# From the root of the zephyr repository
west build -b mimxrt2660_evk/mimxrt2663/cm85 samples/hello_world
west flash -r jlink

Open a serial terminal on the MCU-Link virtual COM port at 115200 8N1, reset the board, and the sample prints:

*** Booting Zephyr OS build v4.5.0 ***
Hello World! mimxrt2660_evk/mimxrt2663/cm85

References

[1] (1,2)

https://www.nxp.com/

Note

The links below point to the NXP website’s landing pages rather than a specific document, because the i.MX RT2660 reference manual and data sheet are not yet published. These links will be updated to the actual documents once NXP publishes them.