RZ/A3M Evaluation Kit
Overview
The EK-RZ/A3M evaluation kit enables users to easily evaluate the features of the RZ/A3M MPU. This kit includes an EK-RZ/A3M board, 5-inch 720x1280 pixel LCD MIPI graphics expansion board, and USB cables, allowing the seamless evaluation of high-definition human machine interface (HMI), camera input through USB, and more features. Equipped with an on-board J-Link debugger, users can conveniently start debugging without additional debuggers. Additionally, it also has several expansion connectors such as SDIO, PMOD,and Arduino to connect sensors, Wi-Fi, and Bluetooth® Low Energy (LE), allowing users to add more features without expanding the board space.
Special Feature Access
MIPI DSI 4 lanes & parallel graphics expansion ports
5-inch MIPI LCD panel (720x1280 pixels)
USB High-Speed Host & Device
32MB External QSPI NOR Flash
128MB External QSPI NAND Flash
External sound codec
External RTC
MPU Native Pin Access
R9A07G066M04GBG MPU
1GHz, Arm Cortex®-A55 core w/NEON extension
Built-in 128MB DDR3L DRAM
128KB SRAM w/ECC
244 pins, BGA package
Native pin access
MPU & USB current measurement
Ecosystem & System Control Access
USB High-Speed Host & Device
5V input through USB (Debug, HS, USB-PD) or external power supply
Debug on-board (Segger J-Link®)
Debug external (SWD & JTAG)
SCIF download (SWD)
3 user LEDs & 2 user buttons
2 SeeedGrove® system (I2C & analog)
2 Digilent Pmod™ (I2C, SPI or UART selectable)
Arduino™ (Uno R3)
MikroElektronika™ mikroBUS
SparkFun® Qwiic® (I2C)
MPU boot configuration switch
Audio In/Out 4-pole
MicroSD card slot
Kit Contents
EK-RZ/A3M board
MIPI graphics expansion board
USB cable (USB C to USB C)
USB cable (USB A female to USB C)
USB cable (USB A male to USB C)
Screw and spacer for fixing the sub board
Hardware
Detailed hardware features for the board can be found at:
Supported Features
The rza3m_ek board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
rza3m_ek/r9a07g066m04gbg target
On-target memory for this board target: 126 MiB of RAM, 32 MiB of Flash.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-A55 CPU1 |
|
Clock control |
on-chip |
Generic fixed-rate clock provider1 |
|
Display |
on-chip |
Renesas LCD controller1 |
|
GPIO & Headers |
on-chip |
Renesas RZ GPIO common1 |
|
on-chip |
|||
on-board |
GPIO pins exposed on Renesas MIPI lcd display headers1 |
||
I2C |
on-chip |
Renesas RZ I2C controller2 |
|
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARM Generic Interrupt Controller v31 |
|
on-chip |
Renesas RZ Interrupt Controller1 |
||
on-chip |
|||
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
MIPI-DSI |
on-chip |
Renesas RZ MIPI DSI host1 |
|
MTD |
on-board |
Flash node1 |
|
Pin control |
on-chip |
Below generic example shows of supported pinctrl definitions:1 |
|
QSPI |
on-chip |
Renesas RZ SPIBSC1 |
|
Serial controller |
on-chip |
||
Timer |
on-chip |
per-core ARM architected timer1 |
Programming and Debugging
The rza3m_ek board supports the runners and associated west commands listed below.
| flash | debug | rtt | debugserver | reset | attach | |
|---|---|---|---|---|---|---|
| jlink | ✅ (default) | ✅ (default) | ✅ | ✅ | ✅ | ✅ |
Applications for the rza3m_ek board can be built, flashed, and debugged in the usual way.
See Building an Application and Run an Application for more details on building and running.
The rza3m_ek board uses Initial Program Loader (IPL) to perform initial settings and
copy the Zephyr image from flash to DDR DRAM for execution.
The board is shipped with the Renesas IPL already programmed, so the IPL build and flash step
below, enabled with -DCONFIG_BUILD_WITH_TFA=y, is optional.
It only needs to be written to flash once, so perform it only if the IPL is corrupted or has to be rewritten.
For the board setup and connections, follow “3.2 Board Setup” of Getting Started with RZ/A Flexible Software Package [4].
Enable the IPL build with
-DCONFIG_BUILD_WITH_TFA=y. The IPL imagerza3m_ek_nor_ipl.srecis generated under zephyr/build/tfa/rza3m_ek_nor/release
# From the root of the zephyr repository
west build -b rza3m_ek samples/hello_world -- -DCONFIG_BUILD_WITH_TFA=y
west flash
Note
Currently, the IPL source code can built on Linux environment only. For Windows, please follow Initial Program Loader Application Note [3]
Console
The UART port is accessed by USB Debug connector (J10).
Debugging
It is possible to load and execute a Zephyr application binary on this board on the Cortex-A55 System Core
from the DDR SDRAM, using JLink debugger (J-Link Debug Host Tools).
Here is an example for building and debugging with the Hello World application.
# From the root of the zephyr repository
west build -b rza3m_ek samples/hello_world
west debug
Flashing
Zephyr application can be flashed to Quad-SPI storage and then loaded by Initial Program Loader.
# From the root of the zephyr repository
west build -b rza3m_ek samples/hello_world
west flash