RA8T2 Evaluation Kit

Board Overview

RA8T2 Evaluation Kit

Name:

ek_ra8t2

Vendor:

Renesas Electronics Corporation

Status:

Maintained

Architecture:

arm

SoC:

r7ka8t2lflcac

Browse board sources

Overview

The EK-RA8T2, an Evaluation Kit for RA8T2 MCU Group, enables users to seamlessly evaluate the features of the RA8T2 MCU group and develop embedded systems applications.

The MCU in this series incorporates a high-performance Arm® Cortex®-M85 core running up to 1 GHz and Arm® Cortex®-M33 core running up to 250 MHz with the following features:

• Up to 1 MB MRAM

• 2 MB SRAM (256 KB of CM85 TCM RAM, 128 KB CM33 TCM RAM, 1664 KB of user SRAM)

• Octal Serial Peripheral Interface (OSPI)

• Layer 3 Ethernet Switch Module (ESWM), USBFS, SD/MMC Host Interface

• Analog peripherals

• Security and safety features

MCU Native Pin Access

• 1 GHz Arm® Cortex®-M85 core and 250 MHz Arm® Cortex®-M33 core based RA8T2 MCU 289 pins, BGA package

• 1 MB MRAM, 2 MB SRAM with ECC

• Native pin access through 2 x 40-pin headers (not populated)

• SDRAM pin access through 2 x 26-pin headers (not populated)

• Ethernet pin access through 4 x 14-pin headers (not populated)

• GPTP pin access through 2 x 5-pin headers (not populated)

• TAS status pin access through 1 x 5-pin headers (not populated)

• MCU current measurement points for precision current consumption measurement

• Multiple clock sources - RA8T2 MCU oscillator and sub-clock oscillator crystals, providing precision 24.000 MHz and 32,768 Hz reference clocks. Additional low-precision clocks are available internal to the RA8T2 MCU

System Control and Ecosystem Access

• USB Full Speed Host and Device (USB-C connector)

• Three 5 V input sources

  • USB (Debug, Full Speed)

  • External power supply (using surface mount clamp test points and power input vias)

• Three Debug modes

  • Debug on-board (SWD and JTAG)

  • Debug in (ETM, SWD, SWO, and JTAG)

  • Debug out (SWD, SWO, and JTAG)

• User LEDs and buttons

  • Three User LEDs (red, blue, green)

  • Power LED (white) indicating availability of regulated power

  • Debug LED (yellow) indicating the debug connection

  • Two User buttons

  • One Reset buttons

• Five most popular ecosystems expansions

  • Two Seeed Grove® system (I2C/I3C/Analog) connectors (not populated)

  • SparkFun® Qwiic® connector (not populated)

  • Two Digilent PmodTM (SPI, UART and I2C) connectors

  • Arduino™ (Uno R3) connector

  • MikroElektronikaTM mikroBUS connector (not populated)

• Combined debugger and MCU boot configuration switches

Special Feature Access

• Ethernet (RJ45 GMII interface) x 2

• PMIC Diagnostic Port pin access through 4-pin header (not populated)

• 64 MB (512 Mb) External Octal-SPI Flash (present in the MCU Native Pin Access area)

• 64 MB (512 Mb) SDRAM (present in the MCU Native Pin Access area)

• Configuration switches

• EtherCAT ID configuration switches and EEPROM

• Ethernet activity LEDs (green x 2, yellow x 2)

• EtherCAT LEDs (red x 1, green x 3)

• Network LEDs (red x 2, green x 2)

• CAN-FD interface x 2

• Isolated MODBUS / RS485 interface

Hardware

Detailed hardware features can be found at:

• RA8T2 MCU: RA8T2 Group User’s Manual Hardware

• EK-RA8T2 board: EK-RA8T2 - User’s Manual

Supported Features

The ek_ra8t2 board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

ek_ra8t2/r7ka8t2lflcac/cm33 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33 CPU1	arm,cortex-m33
CAN	on-chip	Renesas RA CANFD controller global1	renesas,ra-canfd-global
	on-chip	Renesas RA CANFD controller2	renesas,ra-canfd
Clock control	on-chip	Renesas RA Clock Generation Circuit external clock configuration1	renesas,ra-cgc-external-clock
	on-chip	Generic fixed-rate clock provider3	fixed-clock
	on-chip	Renesas RA Sub-Clock1	renesas,ra-cgc-subclk
	on-chip	Renesas RA Clock Generation Circuit PLL Clock2	renesas,ra-cgc-pll
	on-chip	Renesas RA Clock Generation Circuit PLL Clock out line6	renesas,ra-cgc-pll-out
	on-chip	Renesas RA Clock Control node pclk block1	renesas,ra-cgc-pclk-block
	on-chip	Renesas RA Clock Control Peripheral Clock188	renesas,ra-cgc-pclk
	on-chip	Renesas RA External Bus Clock1	renesas,ra-cgc-busclk
Comparator	on-chip	Renesas RA ACMPHS (High-Speed Analog COMParator) Global1	renesas,ra-acmphs-global
	on-chip	Renesas RA ACMPHS (High-Speed Analog COMParator) Controller4	renesas,ra-acmphs
	on-chip	Renesas RA LVD (Low-voltage detection) Controller4	renesas,ra-lvd
Counter	on-chip	Renesas RA AGT as Counter2	renesas,ra-agt-counter
CRC	on-chip	Renesas RA CRC device1	renesas,ra-crc
DMA	on-chip	Renesas RA DMA Controller1	renesas,ra-dma
Ethernet	on-chip	Renesas RA Ethernet MAC Controller1	renesas,ra-eswm
	on-chip	Renesas RA Ethernet MAC Controller2	renesas,ra-ethernet-rmac
	on-chip	Renesas RA External MDIO controller2	renesas,ra-mdio-rmac
Flash controller	on-chip	Renesas RA flash MRAM controller1	renesas,ra-mram-controller
GPIO & Headers	on-chip	Renesas RA GPIO I/O Port113	renesas,ra-gpio-ioport
	on-board	GPIO pins exposed on Mikro BUS headers1	mikro-bus
	on-board	GPIO pins exposed on Arduino Uno (R3) headers1	arduino-header-r3
	on-board	GPIO pins exposed on a Digilent Pmod interface2	digilent,pmod
	on-board	GPIO pins exposed on Grove 4 pins headers2	grove-header
I2C	on-chip	Renesas RA I2C controller3	renesas,ra-iic
	on-chip	Renesas RA SCI-B I2C controller10	renesas,ra-i2c-sci-b
I2S	on-chip	Renesas RA I2S controller2	renesas,ra-i2s-ssie
I3C	on-chip	Renesas RA I3C controller1	renesas,ra-i3c
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	arm,v8m-nvic
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
Mailbox	on-chip	Renesas IPC MBOX2	renesas,ra-ipc-mbox
Memory controller	on-chip	Renesas RA SDRAM controller1	renesas,ra-sdram
Miscellaneous	on-chip	Renesas RA SCI controller19	renesas,ra-sci
	on-chip	Renesas RA AGT2	renesas,ra-agt
	on-chip	Renesas RA ULPT2	renesas,ra-ulpt
	on-chip	Renesas RA External Interrupt131	renesas,ra-external-interrupt
MMU / MPU	on-chip	ARMv8-M MPU (Memory Protection Unit)1	arm,armv8m-mpu
MTD	on-chip	MRAM memory of Renesas RA family2	renesas,ra-nv-mram
PHY	on-chip	This binding is to be used by all the usb transceivers which are built-in with USB IP1	usb-nop-xceiv
Pin control	on-chip	Renesas RA Pin Controller1	renesas,ra-pinctrl-pfs
Power management	on-chip	Renesas RA battery backup domain1	renesas,ra-battery-backup
PWM	on-chip	Renesas RA Pulse Width Modulation14	renesas,ra-pwm
RNG	on-chip	Renesas RA RSIP-E51A TRNG1	renesas,ra-rsip-e50d-trng
RTC	on-chip	Renesas RA RTC1	renesas,ra-rtc
SDHC	on-chip	Renesas RA SDHC2	renesas,ra-sdhc
Serial controller	on-chip	Renesas RA SCI_B UART controller19	renesas,ra8-uart-sci-b
SPI	on-chip	Renesas RA SCI B SPI10	renesas,ra-spi-sci-b
	on-chip	Renesas RA8 SPI_B controller2	renesas,ra8-spi-b
SRAM	on-chip	Generic on-chip SRAM2	mmio-sram
Timer	on-chip	ARMv8-M System Tick1	arm,armv8m-systick
	on-chip	Renesas RA ULPT TIMER2	renesas,ra-ulpt-timer
USB	on-chip	Renesas RA USB full-speed controller1	renesas,ra-usbfs
	on-chip	Renesas RA USB device controller1	renesas,ra-udc
Video	on-chip	Renesas RA Capture Engine Unit Driver (ceu)1	renesas,ra-ceu
Watchdog	on-chip	Renesas RA Watchdog (wdt)1	renesas,ra-wdt

ek_ra8t2/r7ka8t2lflcac/cm85 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M85 CPU1	arm,cortex-m85
CAN	on-chip	Renesas RA CANFD controller global1	renesas,ra-canfd-global
	on-chip	Renesas RA CANFD controller11	renesas,ra-canfd
Clock control	on-chip	Renesas RA Clock Generation Circuit external clock configuration1	renesas,ra-cgc-external-clock
	on-chip	Generic fixed-rate clock provider3	fixed-clock
	on-chip	Renesas RA Sub-Clock1	renesas,ra-cgc-subclk
	on-chip	Renesas RA Clock Generation Circuit PLL Clock2	renesas,ra-cgc-pll
	on-chip	Renesas RA Clock Generation Circuit PLL Clock out line6	renesas,ra-cgc-pll-out
	on-chip	Renesas RA Clock Control node pclk block1	renesas,ra-cgc-pclk-block
	on-chip	Renesas RA Clock Control Peripheral Clock188	renesas,ra-cgc-pclk
	on-chip	Renesas RA External Bus Clock1	renesas,ra-cgc-busclk
Comparator	on-chip	Renesas RA ACMPHS (High-Speed Analog COMParator) Global1	renesas,ra-acmphs-global
	on-chip	Renesas RA ACMPHS (High-Speed Analog COMParator) Controller4	renesas,ra-acmphs
	on-chip	Renesas RA LVD (Low-voltage detection) Controller4	renesas,ra-lvd
Counter	on-chip	Renesas RA AGT as Counter2	renesas,ra-agt-counter
CRC	on-chip	Renesas RA CRC device1	renesas,ra-crc
DMA	on-chip	Renesas RA DMA Controller1	renesas,ra-dma
Ethernet	on-chip	Renesas RA Ethernet MAC Controller1	renesas,ra-eswm
	on-chip	Renesas RA Ethernet MAC Controller2	renesas,ra-ethernet-rmac
	on-chip	Renesas RA External MDIO controller11	renesas,ra-mdio-rmac
	on-board	Single Port Gigabit Ethernet Copper PHY with GMII/RGMII/MII/RMII Interfaces2	microchip,vsc8541
Flash controller	on-chip	Renesas RA flash MRAM controller1	renesas,ra-mram-controller
GPIO & Headers	on-chip	Renesas RA GPIO I/O Port113	renesas,ra-gpio-ioport
	on-board	GPIO pins exposed on Mikro BUS headers1	mikro-bus
	on-board	GPIO pins exposed on Arduino Uno (R3) headers1	arduino-header-r3
	on-board	GPIO pins exposed on a Digilent Pmod interface2	digilent,pmod
	on-board	GPIO pins exposed on Grove 4 pins headers2	grove-header
I2C	on-chip	Renesas RA I2C controller12	renesas,ra-iic
	on-chip	Renesas RA SCI-B I2C controller10	renesas,ra-i2c-sci-b
I2S	on-chip	Renesas RA I2S controller2	renesas,ra-i2s-ssie
I3C	on-chip	Renesas RA I3C controller1	renesas,ra-i3c
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)1	arm,v8.1m-nvic
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
Mailbox	on-chip	Renesas IPC MBOX2	renesas,ra-ipc-mbox
Memory controller	on-chip	Renesas RA SDRAM controller1	renesas,ra-sdram
Miscellaneous	on-chip	Renesas RA SCI controller28	renesas,ra-sci
	on-chip	Renesas RA AGT2	renesas,ra-agt
	on-chip	Renesas RA ULPT2	renesas,ra-ulpt
	on-chip	Renesas RA External Interrupt131	renesas,ra-external-interrupt
MMU / MPU	on-chip	ARMv8.1-M MPU (Memory Protection Unit)1	arm,armv8.1m-mpu
MTD	on-chip	MRAM memory of Renesas RA family2	renesas,ra-nv-mram
	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	fixed-partitions
PHY	on-chip	This binding is to be used by all the usb transceivers which are built-in with USB IP1	usb-nop-xceiv
Pin control	on-chip	Renesas RA Pin Controller1	renesas,ra-pinctrl-pfs
Power management	on-chip	Renesas RA battery backup domain1	renesas,ra-battery-backup
PWM	on-chip	Renesas RA Pulse Width Modulation113	renesas,ra-pwm
RNG	on-chip	Renesas RA RSIP-E51A TRNG1	renesas,ra-rsip-e50d-trng
RTC	on-chip	Renesas RA RTC1	renesas,ra-rtc
SDHC	on-chip	Renesas RA SDHC2	renesas,ra-sdhc
Serial controller	on-chip	Renesas RA SCI_B UART controller28	renesas,ra8-uart-sci-b
SPI	on-chip	Renesas RA SCI B SPI10	renesas,ra-spi-sci-b
	on-chip	Renesas RA8 SPI_B controller11	renesas,ra8-spi-b
SRAM	on-chip	Generic on-chip SRAM2	mmio-sram
Timer	on-chip	ARMv8.1-M System Tick1	arm,armv8.1m-systick
	on-chip	Renesas RA ULPT TIMER2	renesas,ra-ulpt-timer
USB	on-chip	Renesas RA USB full-speed controller1	renesas,ra-usbfs
	on-chip	Renesas RA USB device controller1	renesas,ra-udc
Video	on-chip	Renesas RA Capture Engine Unit Driver (ceu)1	renesas,ra-ceu
Watchdog	on-chip	Renesas RA Watchdog (wdt)1	renesas,ra-wdt

Dual Core Operation

The EK-RA8T2 supports dual core operation with both the Cortex-M85 (CPU0) and Cortex-M33 (CPU1) cores. By default, the CM85 core is the boot core and is responsible for initializing the system and starting the CM33 core.

Memory Usage

By default, MRAM (Flash) and SRAM are split evenly between the two cores. Users can manually change the address and size for MRAM (Flash) and SRAM as follows node:

• CPU0: &code_mram_cm85, &sram0

• CPU1: &code_mram_cm33, &sram1

Note

• MRAM usable range: 0x0200_0000 … 0x0210_0000 (1 MB)

• SRAM usable range: 0x2200_0000 … 0x221A_0000 (1664 KB)

Dual Core Flashing

When flashing or debugging dual-core samples, ensure that CONFIG_SOC_RA_ENABLE_START_SECOND_CORE is selected for the CM85 image. The CM85 core is responsible for starting the CM33 core in soc_late_init_hook.

Programming and Debugging

Applications for the ek_ra8t2 board configuration can be built, flashed, and debugged in the usual way. See Building an Application and Run an Application for more details on building and running.

Here is an example for the Hello World application on CM85 core.

# From the root of the zephyr repository
west build -b ek_ra8t2/r7ka8t2lflcac/cm85 samples/hello_world
west flash

Open a serial terminal, reset the board (press the reset switch), and you should see the following message in the terminal:

***** Booting Zephyr OS v4.2.0-xxx-xxxxxxxxxxxxx *****
Hello World! ek_ra8t2/r7ka8t2lflcac/cm85

For the CM33 core, you can use the --sysbuild flow to build a minimal first-core launcher image that starts the CM33 core.

# From the root of the zephyr repository
west build -b ek_ra8t2/r7ka8t2lflcac/cm33 --sysbuild samples/hello_world
west flash

Flashing

The program can be flashed to EK-RA8T2 via the on-board SEGGER J-Link debugger. SEGGER J-Link’s drivers are available at https://www.segger.com/downloads/jlink/

To flash the program to the board:

1. Connect to J-Link OB via USB port to host PC

2. Make sure J-Link OB jumper is in default configuration as described in EK-RA8T2 - User’s Manual

3. Execute west command

   west flash -r jlink
   

MCUboot bootloader

The sysbuild makes it possible to build and flash all necessary images needed to bootstrap the board.

To build the sample application using sysbuild use the command:

# From the root of the zephyr repository
west build -b ek_ra8t2/r7ka8t2lflcac/cm85 --sysbuild samples/hello_world -- -DSB_CONFIG_BOOTLOADER_MCUBOOT=y
west flash

By default, Sysbuild creates MCUboot and user application images.

Build directory structure created by sysbuild is different from traditional Zephyr build. Output is structured by the domain subdirectories:

build/
├── hello_world
│    └── zephyr
│       ├── zephyr.elf
│       ├── zephyr.hex
│       ├── zephyr.bin
│       ├── zephyr.signed.bin
│       └── zephyr.signed.hex
├── mcuboot
│    └── zephyr
│       ├── zephyr.elf
│       ├── zephyr.hex
│       └── zephyr.bin
└── domains.yaml

Note

With --sysbuild option, MCUboot will be rebuilt and reflashed every time the pristine build is used.

To only flash the user application in subsequent builds, use:

$ west flash --domain hello_world

For more information about the system build please read the Sysbuild (System build) documentation.

You should see the following message in the terminal:

*** Booting MCUboot v2.2.0-171-g8513be710e5e ***
*** Using Zephyr OS build v4.2.0-6183-gdd720e2f0dc5 ***
I: Starting bootloader
I: Image index: 0, Swap type: none
I: Image index: 0, Swap type: none
I: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
I: Boot source: none
I: Image index: 0, Swap type: none
I: Image index: 0, Swap type: none
I: Image index: 0, Swap type: none
I: Image index: 0, Swap type: none
I: Bootloader chainload address offset: 0x10000
I: Image version: v0.0.0
I: Jumping to the first image slot
*** Booting Zephyr OS build v4.2.0-6183-gdd720e2f0dc5 ***
Hello World! ek_ra8t2/r7ka8t2lflcac/cm85

References

• EK-RA8T2 Website

• RA8T2 MCU group Website