RA8D2 Evaluation Kit
Overview
The EK-RA8D2 is an Evaluation Kit for Renesas RA8D2 MCU Group which integrates multiple series of software-compatible Arm®-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development
The MCU in this series incorporates a high-performance Arm® Cortex®-M85 core running up to 1 GHz and Arm® Cortex®-M33 core running up to 250 MHz with the following features:
Up to 1 MB MRAM
2 MB SRAM (256 KB of CM85 TCM RAM, 128 KB CM33 TCM RAM, 1664 KB of user SRAM)
Octal Serial Peripheral Interface (OSPI)
Layer 3 Ethernet Switch Module (ESWM), USBFS, USBHS, SD/MMC Host Interface
Graphics LCD Controller (GLCDC)
2D Drawing Engine (DRW)
MIPI DSI/CSI interface
Analog peripherals
Security and safety features
MCU Native Pin Access
1 GHz Arm® Cortex®-M85 core and 250 MHz Arm® Cortex®-M33 core based RA8D2 MCU in 289 pins, BGA package
1 MB MRAM, 2 MB SRAM with ECC
Native pin access through 2 x 20-pin, and 2 x 40-pin headers (not populated)
Parallel Graphics Expansion Port
Camera Expansion Port (present at the underside of the EK-RA8D2 board)
MIPI Graphics Expansion Port (present at the underside of the EK-RA8D2 board)
MCU current measurement points for precision current consumption measurement
Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing precision 24.000 MHz and 32,768 Hz reference clocks. Additional low-precision clocks are available internal to the RA8D2 MCU
System Control and Ecosystem Access
Four 5 V input sources
USB (Debug, Full Speed, High Speed)
External power supply (using surface mount clamp test points and power input vias)
Three Debug modes
Debug on-board (SWD and JTAG)
Debug in (ETM, SWD, SWO, and JTAG)
Debug out (SWD, SWO, and JTAG)
User LEDs, Status LEDs and switches
Three User LEDs (red, blue, green)
Power LED (white) indicating availability of regulated power.
Debug LED (yellow) indicating the debug connection.
Ethernet LEDs (amber, yellow, green)
Two User switches, One Reset switch
Five most popular ecosystems expansions
Two Seeed Grove® system (I2C/I3C/Analog) connectors (not populated)
SparkFun® Qwiic® connector (not populated)
Two Digilent PmodTM (SPI, UART and I2C) connectors
Arduino™ (Uno R3) connector
MikroElektronikaTM mikroBUS™ connector (not populated)
USB Full Speed Host and Device (USB-C connector)
MCU boot configuration jumper
Special Feature Access
USB High Speed Host and Device (USB-C connector)
Ethernet (RJ45 RGMII interface)
64 MB (512 Mb) External Octo-SPI Flash (present in the MCU Native Pin Access area)
64 MB (512 Mb) SDRAM (present in the MCU Native Pin Access area)
PDM MEMS Microphones (present at the underside of the EK-RA8D2 board)
Audio CODEC with speaker out connections
Configuration switches
Hardware
Detailed hardware features can be found at:
RA8D2 MCU: RA8D2 Group User’s Manual Hardware
EK-RA8D2 board: EK-RA8D2 - User’s Manual
Supported Features
The ek_ra8d2 board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
ek_ra8d2/r7ka8d2kflcac/cm85 target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M85 CPU1 |
|
CAN |
on-chip |
Renesas RA CANFD controller global1 |
|
on-chip |
Renesas RA CANFD controller2 |
||
Clock control |
on-board |
An external clock signal driven by a PWM pin1 |
|
on-chip |
Renesas RA Clock Generation Circuit external clock configuration1 |
||
on-chip |
Generic fixed-rate clock provider3 |
||
on-chip |
Renesas RA Sub-Clock1 |
||
on-chip |
Renesas RA Clock Generation Circuit PLL Clock2 |
||
on-chip |
Renesas RA Clock Generation Circuit PLL Clock out line6 |
||
on-chip |
Renesas RA Clock Control node pclk block1 |
||
on-chip |
|||
on-chip |
Renesas RA External Bus Clock1 |
||
Comparator |
on-chip |
Renesas RA ACMPHS (High-Speed Analog COMParator) Global1 |
|
on-chip |
Renesas RA ACMPHS (High-Speed Analog COMParator) Controller4 |
||
on-chip |
Renesas RA LVD (Low-voltage detection) Controller4 |
||
Counter |
on-chip |
Renesas RA AGT as Counter2 |
|
CRC |
on-chip |
Renesas RA CRC device1 |
|
Display |
on-chip |
Renesas Graphic LCD controller1 |
|
DMA |
on-chip |
Renesas RA DMA Controller1 |
|
Flash controller |
on-chip |
Renesas RA flash MRAM controller1 |
|
GPIO & Headers |
on-chip |
||
on-board |
GPIO pins exposed on Mikro BUS headers1 |
||
on-board |
ArduCam FFC 40-pin camera connector.1 |
||
I2C |
on-chip |
Renesas RA I2C Master controller3 |
|
on-chip |
Renesas RA SCI-B I2C controller10 |
||
I2S |
on-chip |
Renesas RA I2S controller2 |
|
I3C |
on-chip |
Renesas RA I3C controller1 |
|
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
Memory controller |
on-chip |
Renesas RA SDRAM controller1 |
|
Miscellaneous |
on-chip |
||
on-chip |
Renesas RA AGT2 |
||
on-chip |
Renesas RA ULPT2 |
||
on-chip |
|||
MMU / MPU |
on-chip |
ARMv8.1-M MPU (Memory Protection Unit)1 |
|
MTD |
on-chip |
MRAM memory of Renesas RA family1 |
|
on-board |
Fixed partitions of a flash (or other non-volatile storage) memory1 |
||
PHY |
on-chip |
This binding is to be used by all the usb transceivers which are built-in with USB IP1 |
|
on-chip |
Renesas RA USBHS internal PHY controller1 |
||
Pin control |
on-chip |
Renesas RA Pin Controller1 |
|
Power management |
on-chip |
Renesas RA battery backup domain1 |
|
PWM |
on-chip |
||
RTC |
on-chip |
Renesas RA RTC1 |
|
SDHC |
on-chip |
Renesas RA SDHC2 |
|
Serial controller |
on-chip |
||
SPI |
on-chip |
Renesas RA8 SPI_B controller2 |
|
SRAM |
on-chip |
Generic on-chip SRAM1 |
|
Timer |
on-chip |
ARMv8.1-M System Tick1 |
|
on-chip |
Renesas RA ULPT TIMER2 |
||
USB |
on-chip |
Renesas RA USB full-speed controller1 |
|
on-chip |
|||
on-chip |
Renesas RA USB high-speed controller1 |
||
Video |
on-chip |
Renesas RA Capture Engine Unit Driver (ceu)1 |
|
Watchdog |
on-chip |
Renesas RA Watchdog (wdt)1 |
Note
For using the Camera Expansion Port (J35) in DVP interface, please set switch SW4 as following configuration:
SW4-1 PMOD1
SW4-2 PMOD1
SW4-3 Octo-SPI
SW4-4 Arduino
SW4-5 I3C
SW4-6 MIPI
SW4-7 USBFS
SW4-8 USBHS
OFF
ON
Programming and Debugging
The ek_ra8d2 board supports the runners and associated west commands listed below.
| flash | debug | attach | rtt | debugserver | |
|---|---|---|---|---|---|
| jlink | ✅ (default) | ✅ (default) | ✅ | ✅ | ✅ |
| pyocd | ✅ | ✅ | ✅ | ✅ | ✅ |
Applications for the ek_ra8d2 board configuration can be
built, flashed, and debugged in the usual way. See
Building an Application and Run an Application for more details on
building and running.
Here is an example for the Hello World application on CM85 core.
# From the root of the zephyr repository
west build -b ek_ra8d2/r7ka8d2kflcac/cm85 samples/hello_world
west flash
Open a serial terminal, reset the board (Pressing the reset switch SW3), and you should see the following message in the terminal:
***** Booting Zephyr OS v4.2.0-xxx-xxxxxxxxxxxxx *****
Hello World! ek_ra8d2/r7ka8d2kflcac/cm85
Flashing
Program can be flashed to EK-RA8D2 via the on-board SEGGER J-Link debugger. SEGGER J-link’s drivers are available at https://www.segger.com/downloads/jlink/
To flash the program to board
Connect to J-Link OB via USB port to host PC
Make sure J-Link OB jumper is in default configuration as described in EK-RA8D2 - User’s Manual
Execute west command
west flash -r jlink
MCUboot bootloader
The sysbuild makes possible to build and flash all necessary images needed to bootstrap the board.
To build the sample application using sysbuild use the command:
# From the root of the zephyr repository
west build -b ek_ra8d2/r7ka8d2kflcac/cm85 --sysbuild samples/hello_world -- -DSB_CONFIG_BOOTLOADER_MCUBOOT=y
west flash
By default, Sysbuild creates MCUboot and user application images.
Build directory structure created by sysbuild is different from traditional Zephyr build. Output is structured by the domain subdirectories:
build/
├── hello_world
| └── zephyr
│ ├── zephyr.elf
│ ├── zephyr.hex
│ ├── zephyr.bin
│ ├── zephyr.signed.bin
│ └── zephyr.signed.hex
├── mcuboot
│ └── zephyr
│ ├── zephyr.elf
│ ├── zephyr.hex
│ └── zephyr.bin
└── domains.yaml
Note
With --sysbuild option, MCUboot will be rebuilt and reflashed
every time the pristine build is used.
To only flash the user application in the subsequent builds, Use:
$ west flash --domain hello_world
For more information about the system build please read the Sysbuild (System build) documentation.
You should see the following message in the terminal:
*** Booting MCUboot v2.2.0-171-g8513be710e5e ***
*** Using Zephyr OS build v4.2.0-6343-g2ce9ea10e7df ***
I: Starting bootloader
I: Image index: 0, Swap type: none
I: Image index: 0, Swap type: none
I: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
I: Boot source: none
I: Image index: 0, Swap type: none
I: Image index: 0, Swap type: none
I: Image index: 0, Swap type: none
I: Image index: 0, Swap type: none
I: Bootloader chainload address offset: 0x10000
I: Image version: v0.0.0
I: Jumping to the first image slot
*** Booting Zephyr OS build v4.2.0-6343-g2ce9ea10e7df ***
Hello World! ek_ra8d2/r7ka8d2kflcac/cm85