STM32MP215F-DK Evaluation Board

Overview

The STM32MP215F-DK Discovery kit is designed as a complete demonstration and development platform for the STMicroelectronics STM32MP215F microprocessor based on the Arm® Cortex®-A35 (1.5 GHz) and Cortex®-M33 processors. Zephyr OS is ported to run on the Cortex®-M33 core, as a coprocessor of the Cortex®-A35 core.

Features:

  • STM32MP215FAN3 microprocessor based on the Arm® Cortex®-A35 up to 1.5 GHz and Cortex®-M33 at 300 MHz in a VFBGA273 package

  • STMicroelectronics power management STPMIC2L

  • 16-Gbit LPDDR4 DRAM

  • 100-Mbit/s Ethernet (RMII)

  • USB 2.0 Bus Powered

  • Four user LEDs

  • Two user, one tamper, and one reset push-buttons

  • Wake-up button

  • Four boot pin switches

  • Board connectors:

    • Ethernet RJ45

    • USB 2.0 USB Type-C®

    • microSD™ card holder

    • Dual-lane MIPI CSI-2® camera module expansion connector

    • LTDC display connector

    • M.2 E-Key connector to support Wi-Fi® and Bluetooth® SDIO modules

    • GPIO expansion connector

    • VBAT for power backup

    • MIPI10 JTAG connector

    • STDC14 connector for debug

  • Mainlined open-source Linux® STM32 MPU OpenSTLinux Distribution and STM32CubeMP2 software with examples

  • Linux® Yocto Project®, Buildroot, and STM32CubeIDE as development environments

More information about the board can be found at the STM32MP215F-DK website [1].

Hardware

Cores:

  • 64-bit single-core Arm® Cortex®-A35 - Up to 1.5 GHz - 32-Kbyte I + 32-Kbyte D level 1 cache for each core - 128-Kbyte level 2 cache - Arm® NEON™ and Arm® TrustZone®

  • 32-bit Arm® Cortex®-M33 with FPU/MPU - Up to 300 MHz - L1 16-Kbyte I / 16-Kbyte D - Arm® TrustZone®

Memories:

  • External DDR memory up to 4 Gbytes - DDR3L-1600 16-bit - DDR4-1600 16-bit - LPDDR4-1600 16-bit

  • 456-Kbyte internal SRAM: 256-Kbyte AXI SYSRAM, 64-Kbyte AHB SRAM, 128-Kbyte AHB SRAM with ECC in backup domain, 8-Kbyte SRAM with ECC in backup domain

  • One Octo-SPI memory interfaces

  • Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs, and SLC NAND memories with up to 8-bit ECC

Security/safety:

  • Secure boot, TrustZone® peripherals, active tamper, environmental monitors, display secure layer, hardware accelerators

  • Complete resource isolation framework

Reset and power management:

  • 1.71 to 1.95 V and 2.7/3.0 to 3.6 V multiple section I/O supply

  • POR, PDR, PVD, and BOR

  • On-chip LDO and power-switches for RETRAM, BKPSRAM, and VSW

  • Dedicated supplies for Cortex®-A35

  • Internal temperature sensor

  • Low-power modes: Sleep, Stop, and Standby

  • DDR memory retention in Standby mode

  • Controls for PMIC companion chip

Clock management:

  • Internal oscillators: 64 MHz HSI, 16 MHz MSI, 32 kHz LSI

  • External oscillators: 16-48 MHz HSE, 32.768 kHz LSE

  • Up to 7x PLLs with fractional mode General-purpose inputs/outputs

  • Up to 123 secure I/O ports with interrupt capability

  • Up to six wake-up inputs

  • Up to seven tamper input pins + 5 active tampers output pins Interconnect matrix

  • Bus matrices

  • 128-, 64-, 32-bit STNoC interconnect, up to 600 MHz

  • 32-bit Arm® AMBA® AHB interconnect, up to 300 MHz

  • 3 DMA controllers to unload the CPU

  • 48 physical channels in total

  • 3x dual master port, high-performance, general-purpose, direct memory access controller (HPDMA), 16 channels each

Up to 37 communication peripherals:

  • 3x I2C FM+ (1 Mbit/s, SMBus/PMBus®)

  • 3x I3C (12.5 Mbit/s)

  • 3x UART + 4x USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI) + 1x LPUART

  • 6x SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy via internal audio PLL or external clock)(+1 with OCTOSPI + 4 with USART)

  • 4x SAI (stereo audio: I2S, PDM, SPDIF Tx)

  • SPDIF Rx with four inputs

  • 3x SDMMC up to 8-bit (SD/eMMC™/SDIO)

  • Up to 2x CAN controllers supporting CAN FD protocol, out of which one supports time-triggered CAN (TTCAN)

  • 1x USB 2.0 high-speed Host with embedded 480 Mbits/s PHY

  • 1x USB 2.0 high-speed dual role data with embedded 480 Mbits/s PHY

  • Up to 2x Gigabit Ethernet interfaces

  • TSN, IEEE 1588v2 hardware, MII/RMII/RGMII

  • Camera interface #1 (5 Mpixels at 30 fps)

  • MIPI CSI-2®, 2x data lanes up to 2.5 Gbit/s each

  • 8- to 16-bit parallel, up to 120 MHz

  • RGB, YUV, JPG, RawBayer with light ISP

  • Lite-ISP, demosaicing, downscaling, cropping, 3 pixel pipelines

  • Camera interface #2 (1 Mpixels at 15 fps)

  • 8- to 14-bit parallel, up to 80 MHz

  • RGB, YUV, JPG

  • Cropping

  • Digital parallel interface up to 16-bit input or output

5 analog peripherals:

  • 2x ADCs with 12-bit max. resolution (up to 5 Msps each, up to 23 channels)

  • Internal temperature sensor (DTS)

  • 1x multifunction digital filter (MDF) with up to 4 channels/4 filters

  • Internal (VREFBUF) or external ADC reference VREF+

Graphics:

  • LCD-TFT controller, up to 24-bit // RGB888

  • Up to FHD (1920 x 1080) at 60 fps

  • 3 layers including a secure layer

  • YUV support

Up to 28 timers and 5 watchdogs:

  • 4x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

  • 2x 16-bit advanced motor control timers

  • 10x 16-bit general-purpose timers (including 2 basic timers without PWM)

  • 5x 16-bit low-power timers

  • Secure RTC with subsecond accuracy and hardware calendar

  • 4 Cortex®-A35 system timers (secure, nonsecure, virtual, hypervisor)

  • 2x SysTick Cortex®-M33 timer (secure, nonsecure)

  • 5x watchdogs (4x independent and 1x window)

Hardware acceleration:

  • 2x cryptographic processors (CRYP), AES-128, -192, -256, DES/TDES

  • Secure AES-256 with SCA

  • RSA, ECC, ECDSA with SCA

  • 2x HASH (SHA-1, SHA-224, SHA-256, SHA3), HMAC

  • 2x true random number generator

  • CRC calculation unit

  • “On-the-fly” DDR encryption/decryption (AES-128, AES-256)

  • “On-the-fly” OTFDEC Octo-SPI flash memory decryption (AES-128)

Debug mode:

  • Arm® CoreSight™ trace and debug: SWD and JTAG interfaces

More information about STM32MP215F can be found here:

Supported Features

The stm32mp215f_dk board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

stm32mp215f_dk/stm32mp215fxx/m33 target

Type

Location

Description

Compatible

CPU

on-chip

ARM Cortex-M33 CPU1

arm,cortex-m33

CAN

on-chip

STM32H7 series (and compatible) FDCAN CAN FD controller2

st,stm32h7-fdcan

Clock control

on-chip

STM32MP2 RCC (Reset and Clock controller)1

st,stm32mp2-rcc

on-chip

Generic fixed-rate clock provider2

fixed-clock

GPIO & Headers

on-chip

STM32MP2 GPIO Controller12

st,stm32mp2-gpio

I2C

on-chip

STM32 I2C V2 controller3

st,stm32-i2c-v2

I3C

on-chip

STM32H5 I3C controller3

st,stm32-i3c

Input

on-board

Group of GPIO-bound input keys1

gpio-keys

Interrupt controller

on-chip

ARMv8-M NVIC (Nested Vectored Interrupt Controller)1

arm,v8m-nvic

on-chip

STM32 External Interrupt Controller1

st,stm32-exti

IPM

on-chip

STM32 IPCC MAILBOX1

st,stm32-ipcc-mailbox

LED

on-board

Group of GPIO-controlled LEDs1

gpio-leds

Pin control

on-chip

STM32 Pin controller1

st,stm32-pinctrl

Reset controller

on-chip

STM32 Reset and Clock Control (RCC) Controller1

st,stm32-rcc-rctl

Serial controller

on-chip

STM32 USART4

st,stm32-usart

on-chip

STM32 UART12

st,stm32-uart

SPI

on-chip

STM32H7 SPI controller15

st,stm32h7-spi

Timer

on-chip

ARMv8-M System Tick1

arm,armv8m-systick

Watchdog

on-chip

STM32 watchdog1

st,stm32-watchdog

on-chip

STM32 system window watchdog1

st,stm32-window-watchdog

Connections and IOs

STM32MP215F-DK Evaluation Board schematic is not yet available.

System Clock

Cortex®-A35

Not yet supported in Zephyr.

Cortex®-M33

The Cortex®-M33 Core is configured to run at a 300 MHz clock speed.

Programming and Debugging

The stm32mp215f_dk board supports the runners and associated west commands listed below.

flash debug attach rtt debugserver
openocd ✅ (default) ✅ (default) ✅ ✅ ✅

Prerequisite

Before you can run Zephyr on the STM32MP215F-DK Discovery kit, you need to set up the Cortex®-A35 core with a Linux® environment. The Cortex®-M33 core runs Zephyr as a coprocessor, and it requires the Cortex®-A35 to load and start the firmware using remoteproc.

One way to set up the Linux environment is to use the official ST OpenSTLinux distribution, following the Starter Package [4]. (more information about the procedure can be found in the STM32MPU Wiki [5])

Loading the firmware

Once the OpenSTLinux distribution is installed on the board, the Cortex® -A35 is responsible (in the current distribution) for loading the Zephyr firmware image in DDR and/or SRAM and starting the Cortex®-M33 core. The application can be built using west, taking the Blinky as an example.

# From the root of the zephyr repository
west build -b stm32mp215f_dk/stm32mp215fxx/m33 samples/basic/blinky

The firmware can be copied to the board file system and started with the Linux remoteproc framework. (more information about the procedure can be found in the STM32MP215F boot Cortex-M33 firmware [3])

Debugging

Applications can be debugged using OpenOCD and GDB. The OpenOCD files can be found at device-stm-openocd [6]. The firmware must first be started by the Cortex®-A35. The debugger can then be attached to the running Zephyr firmware using OpenOCD.

  • Build the sample:

# From the root of the zephyr repository
west build -b stm32mp215f_dk/stm32mp215fxx/m33 samples/basic/blinky

$ west attach

References