This is the documentation for the latest (main) development branch of Zephyr. If you are looking for the documentation of previous releases, use the drop-down menu on the left and select the desired version.

ST Nucleo H533RE


The Nucleo H533RE board is designed as an affordable development platform for STMicroelectronics ARM® Cortex®-M33 core-based STM32H533RET6 microcontroller with TrustZone®. Here are some highlights of the Nucleo H533RE board:

  • STM32H533RE microcontroller featuring 512 kbytes of Flash memory and 272 Kbytes of SRAM in LQFP64 package

  • Board connectors:

    • USB Type-C™ Sink device FS

    • ST Zio expansion connector including Arduino Uno V3 connectivity (CN5, CN6, CN8, CN9)

    • ST morpho extension connector (CN7, CN10)

  • Flexible board power supply:

    • 5V_USB_STLK from ST-Link USB connector

    • VIN (7 - 12V, 0.8) supplied via pin header CN6 pin 8 or CN7 pin 24

    • ESV on the ST morpho connector CN7 Pin 6 (5V, O.5A)

    • VBUS_STLK from a USB charger via the ST-LINK USB connector

    • VBUSC from the USB user connector (5V, 0.5A)

    • 3V3_EXT supplied via a pin header CN6 pin 4 or CN7 pin 16 (3.3V, 1.3A)

  • On-board ST-LINK/V3EC debugger/programmer

    • mass storage

    • Virtual COM port

    • debug port

  • One user LED shared with ARDUINO® Uno V3

  • Two push-buttons: USER and RESET

  • 32.768 kHz crystal oscillator

More information about the board can be found at the NUCLEO_H533RE website.



The STM32H533xx devices are high-performance microcontrollers from the STM32H5 Series based on the high-performance Arm® Cortex®-M33 32-bit RISC core. They operate at a frequency of up to 250 MHz.

  • Core: ARM® 32-bit Cortex® -M33 CPU with TrustZone® and FPU.

  • Performance benchmark:

    • 375 DMPIS/MHz (Dhrystone 2.1)

  • Security

    • Arm® TrustZone® with Armv8-M mainline security extension

    • Up to eight configurable SAU regions

    • TrustZone® aware and securable peripherals

    • Flexible life cycle scheme with secure debug authentication

    • SESIP3 and PSA Level 3 certified assurance target

    • Preconfigured immutable root of trust (ST-iROT)

    • SFI (secure firmware installation)

    • Root of trust thanks to unique boot entry and secure hide protection area (HDP)

    • Secure data storage with hardware unique key (HUK)

    • Secure firmware upgrade support with TF-M

    • Two AES coprocessors including one with DPA resistance

    • Public key accelerator, DPA resistant

    • On-the-fly decryption of Octo-SPI external memories

    • HASH hardware accelerator

    • True random number generator, NIST SP800-90B compliant

    • 96-bit unique ID

    • Active tampers

  • Clock management:

    • 24 MHz crystal oscillator (HSE)

    • 32 kHz crystal oscillator for RTC (LSE)

    • Internal 64 MHz (HSI) trimmable by software

    • Internal low-power 32 kHz RC (LSI)( ±5%)

    • Internal 4 MHz oscillator (CSI), trimmable by software

    • Internal 48 MHz (HSI48) with recovery system

    • 3 PLLs for system clock, USB, audio, ADC

  • Power management

    • Embedded regulator (LDO) with three configurable range output to supply the digital circuitry

    • Embedded SMPS step-down converter

  • RTC with HW calendar, alarms and calibration

  • Up to 112 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V

  • Up to 16 timers and 2 watchdogs

    • 8x 16-bit

    • 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

    • 2x 16-bit low-power 16-bit timers (available in Stop mode)

    • 2x watchdogs

    • 2x SysTick timer

  • Memories

    • Up to 512 Kbytes Flash, 2 banks read-while-write

    • 1 Kbyte OTP (one-time programmable)

    • 272 Kbytes of SRAM (80-Kbyte SRAM2 with ECC)

    • 2 Kbytes of backup SRAM available in the lowest power modes

    • Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, NOR/NAND memories

    • 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats

    • 1x SD/SDIO/MMC interfaces

  • Rich analog peripherals (independent supply)

    • 2x 12-bit ADC with up to 5 MSPS in 12-bit

    • 1x 12-bit DAC with 2 channels

    • 1x Digital temperature sensor

    • Voltage reference buffer

  • 34x communication interfaces

    • 1x USB Type-C / USB power-delivery controller

    • 1x USB 2.0 full-speed host and device (crystal-less)

    • 3x I2C FM+ interfaces (SMBus/PMBus)

    • 2x I3C interface

    • 6x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control)

    • 1x LP UART

    • 4x SPIs including 3 muxed with full-duplex I2S

    • 4x additional SPI from 4x USART when configured in Synchronous mode

    • 2x FDCAN

    • 1x SDMMC interface

    • 2x 16 channel DMA controllers

    • 1x 8- to 14- bit camera interface

    • 1x HDMI-CEC

    • 1x 16-bit parallel slave synchronous-interface

  • Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™

More information about STM32H533RE can be found here:

Supported Features

The Zephyr nucleo_h533re board configuration supports the following hardware features:






reset and clock control






nested vector interrupt controller









True Random number generator



Real Time Clock



serial port-polling; serial port-interrupt



independent watchdog

Other hardware features are not yet supported on this Zephyr port.

The default configuration can be found in the defconfig and dts files:

Zephyr board options

The STM32H533 is a SoC with Cortex-M33 architecture. Zephyr provides support for building for Secure firmware.

The BOARD options are summarized below:




For building Secure firmware

Connections and IOs

Nucleo H533RE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, input/output, pull-up, etc.

For more details please refer to STM32H5 Nucleo-64 board User Manual.

Default Zephyr Peripheral Mapping:

  • ADC1 channel 14 input: PB1

  • USART1 TX/RX : PB14/PB15 (Arduino USART1)


  • UART2 TX/RX : PA2/PA3 (VCP)

  • USER_PB : PC13

System Clock

Nucleo H533RE System Clock could be driven by internal or external oscillator, as well as main PLL clock. By default System clock is driven by PLL clock at 240MHz, driven by an 24MHz high-speed external clock.

Serial Port

Nucleo H533RE board has up to 6 U(S)ARTs. The Zephyr console output is assigned to USART2. Default settings are 115200 8N1.

Programming and Debugging

Applications for the nucleo_h533re board can be built and flashed in the usual way (see Building an Application and Run an Application for more details).


Nucleo H533RE board includes an ST-LINK/V3EC embedded debug tool interface. This probe allows to flash the board using various tools.

Board is configured to be flashed using west STM32CubeProgrammer runner. Installation of STM32CubeProgrammer is then required to flash the board.

Alternatively, pyocd or jlink via an external probe can also be used to flash and debug the board if west is told to use it as runner, which can be done by passing either or -r pyocd, or -r jlink.

For pyocd additional target information needs to be installed. This can be done by executing the following commands.

$ pyocd pack --update
$ pyocd pack --install stm32h5

Flashing an application to Nucleo H533RE

Connect the Nucleo H533RE to your host computer using the USB port. Then build and flash an application. Here is an example for the Hello World application.

Run a serial host program to connect with your Nucleo board:

$ minicom -D /dev/ttyACM0

Then build and flash the application.

# From the root of the zephyr repository
west build -b nucleo_h533re samples/hello_world
west flash

You should see the following message on the console:

Hello World! nucleo_h533re


You can debug an application in the usual way. Here is an example for the Blinky application.

# From the root of the zephyr repository
west build -b nucleo_h533re samples/basic/blinky
west debug