STM32H5F5J-DK Discovery
Overview
The STM32H5F5J-DK Discovery kit is designed as a complete demonstration and development platform for STMicroelectronics Arm® Cortex®‑M33 core-based STM32H5F5LJH7Q microcontroller with TrustZone®. Here are some highlights of the STM32H5F5J-DK Discovery board:
STM32H5F5LJH7Q microcontroller featuring 4 Mbytes of Flash memory and 1.5 Mbytes of SRAM in TFBGA225 package
4.3” RGB 480X572pixels TFT colored LCD module and touch panel
USB Type-C® Full-Speed device with USB power-delivery sink only controller
SAI Audio DAC stereo with one audio jacks for input/output,
ST MEMS digital microphone with PDM interface
Octo-SPI interface connected to 512Mbit Octo-SPI NORFlash memory device (MX25LM51245GXDI00 from MACRONIX)
Octo-SPI interface connected to 64Mbit Octo-SPI SRAM memory.
10/100-Mbit Ethernet,
microSD™
A Wi‑Fi® add-on board
Board connectors
STMod+ expansion connector with fan-out expansion board for Wi‑Fi®, Grove and mikroBUS™ compatible connectors
Pmod™ expansion connector
Audio MEMS daughterboard expansion connector
ARDUINO® Uno V3 expansion connector
Flexible power-supply options
ST-LINK
USB VBUS
external sources
On-board STLINK-V3E debugger/programmer with USB re-enumeration capability:
mass storage
Virtual COM port
debug port
4 user LEDs
User and reset push-buttons
More information about the board can be found at the STM32H5F5J-DK Discovery website.
Hardware
The STM32H5F5xx devices are an high-performance microcontrollers family (STM32H5 Series) based on the high-performance Arm® Cortex®‑M33 32-bit RISC core. They operate at a frequency of up to 250 MHz.
Core: Arm® 32-bit Cortex®-M33 CPU with TrustZone® and FPU.
Performance benchmark:
375 DMPIS/MHz (Dhrystone 2.1)
Security
Arm® Cortex®‑M33 TrustZone® with ARMv8-M mainline security extension
Up to 8 configurable SAU regions
TrustZone® aware and securable peripherals
Flexible lifecycle scheme with secure debug authentication
Preconfigured immutable root of trust (ST-iROT)
SFI (secure firmware installation)
Secure data storage with hardware unique key (HUK)
Secure firmware upgrade support with TF-M
2x AES coprocessors including one with DPA resistance
Public key accelerator, DPA resistant
On-the-fly decryption of Octo-SPI external memories
HASH hardware accelerator
True random number generator, NIST SP800-90B compliant
96-bit unique ID
Active tampers
True Random Number Generator (RNG) NIST SP800-90B compliant
Clock management:
48 MHz crystal oscillator (HSE)
32768 Hz crystal oscillator for RTC (LSE)
Internal 64 MHz (HSI) trimmable by software
Internal low-power 32 kHz RC (LSI)( ±5%)
Internal 4 MHz oscillator (CSI), trimmable by software
Internal 48 MHz (HSI48) with recovery system
3 PLLs for system clock, USB, audio, ADC
Power management
Embedded regulator (LDO) with three configurable range output to supply the digital circuitry
Embedded SMPS step-down converter
RTC with HW calendar, alarms and calibration
Up to 178 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V
Up to 24 timers and 2 watchdogs
12x 16-bit
2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
6x 16-bit low-power 16-bit timers (available in Stop mode)
2x watchdogs
2x SysTick timer
Memories
Up to 4 MB Flash, 2 banks read-while-write
2 Kbyte OTP (one-time programmable)
1536 KB of contiguous SRAM including 384 Kbytes with flexible ECC
4 Kbytes of backup SRAM available in the lowest power modes
Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
2x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats
2x SD/SDIO/MMC interfaces
Rich analog peripherals (independent supply)
3x 12-bit ADC with up to 5 MSPS in 12-bit
2x 12-bit D/A converters
1x Digital temperature sensor
37x communication interfaces
1x USB Type-C®/USB Power Delivery r3.1
1x USB OTG full-speed
1x USB OTG high-speed with embedded PHY
4x I2C FM+ interfaces (SMBus/PMBus)
2x I3C interface
12x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control)
1x LP UART
6x SPIs including 3 muxed with full-duplex I2S
5x additional SPI from 5x USART when configured in Synchronous mode
2x SAI
3x FDCAN
1x SDMMC interface
2x 16 channel DMA controllers
1x 8- to 14- bit camera interface
1x HDMI-CEC
1x Ethernel MAC interface with DMA controller
1x 16-bit parallel slave synchronous-interface
CORDIC for trigonometric functions acceleration
FMAC (filter mathematical accelerator)
CRC calculation unit
Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™
More information about STM32H5F5 can be found here:
Supported Features
The stm32h5f5j_dk board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
stm32h5f5j_dk/stm32h5f5xx target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M33 CPU1 |
|
ADC |
on-chip |
||
CAN |
on-chip |
STM32 FDCAN CAN FD controller3 |
|
Clock control |
on-chip |
STM32H5 RCC (Reset and Clock controller)1 |
|
on-chip |
STM32 HSE Clock1 |
||
on-chip |
STM32 HSI Clock1 |
||
on-chip |
|||
on-chip |
STM32 LSE Clock1 |
||
on-chip |
|||
on-chip |
STM32 Microcontroller Clock Output (MCO)2 |
||
Counter |
on-chip |
STM32 counters14 |
|
CRC |
on-chip |
STM32 CRC calculation unit1 |
|
Cryptographic accelerator |
on-chip |
STM32 AES Accelerator1 |
|
DAC |
on-chip |
STM32 family DAC1 |
|
DMA |
on-chip |
STM32U5 DMA controller2 |
|
Ethernet |
on-chip |
STM32 Ethernet Controller1 |
|
on-chip |
STM32H5 Ethernet1 |
||
on-chip |
STM32 MDIO Controller1 |
||
Flash controller |
on-chip |
STM32 Family flash controller1 |
|
on-board |
STM32 XSPI Flash controller supporting the JEDEC CFI interface1 |
||
GPIO & Headers |
on-chip |
STM32 GPIO Controller11 |
|
on-board |
GPIO pins exposed on Arduino Uno (R3) headers1 |
||
I2C |
on-chip |
||
I2S |
on-chip |
STM32H7 I2S controller3 |
|
on-chip |
STM32 SAI controller2 |
||
I3C |
on-chip |
STM32H5 I3C controller2 |
|
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv8-M NVIC (Nested Vectored Interrupt Controller)1 |
|
on-chip |
STM32G0 External Interrupt Controller1 |
||
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
on-board |
Group of PWM-controlled LEDs1 |
||
Memory controller |
on-chip |
STM32 Flexible Memory Controller (FMC)1 |
|
on-board |
STM32 XSPI PSRAM1 |
||
MMC |
on-chip |
STM32 SDMMC Disk Access2 |
|
MMU / MPU |
on-chip |
ARMv8-M MPU (Memory Protection Unit)1 |
|
MTD |
on-chip |
STM32 flash memory1 |
|
on-board |
Fixed partitions of a flash (or other non-volatile storage) memory1 |
||
on-board |
Flash node1 |
||
NVMEM |
on-chip |
Fixed layout for Non-Volatile memory1 |
|
OTP memory |
on-chip |
||
PHY |
on-chip |
This binding is to be used by all the usb transceivers which are built-in with USB IP1 |
|
Pin control |
on-chip |
STM32 Pin controller1 |
|
Power management |
on-chip |
STM32H5 I/O cell controller1 |
|
PWM |
on-chip |
||
Regulator |
on-chip |
STM32 VREFBUF regulator1 |
|
Reset controller |
on-chip |
STM32 Reset and Clock Control (RCC) Controller1 |
|
RNG |
on-chip |
STM32 Random Number Generator1 |
|
RTC |
on-chip |
STM32 RTC1 |
|
Sensors |
on-chip |
STM32 Digital Temperature Sensor1 |
|
on-chip |
STM32 family TEMP node for production calibrated sensors with two calibration temperatures1 |
||
on-chip |
STM32 VREF+1 |
||
on-chip |
STM32 VBAT1 |
||
Serial controller |
on-chip |
||
on-chip |
STM32 LPUART1 |
||
on-chip |
|||
SMbus |
on-chip |
STM32 SMBus controller4 |
|
SPI |
on-chip |
||
Timer |
on-chip |
ARMv8-M System Tick1 |
|
on-chip |
STM32 low-power timer (LPTIM)6 |
||
on-chip |
|||
USB |
on-chip |
STM32 USB controller1 |
|
Watchdog |
on-chip |
STM32 watchdog1 |
|
on-chip |
STM32 system window watchdog1 |
||
xSPI |
on-chip |
STM32 XSPI Controller2 |
Connections and IOs
STM32H5F5J-DK Discovery Board has 9 GPIO controllers. These controllers are responsible for pin muxing, input/output, pull-up, etc.
For more details please refer to STM32H5F5J-DK Discovery board User Manual.
Default Zephyr Peripheral Mapping:
USART_2 TX/RX : PA2/PA3 (VCP)
UART_7 TX/RX : PE8/PE7 (ARDUINO® UART7)
USER_PB : PI8
LD1 (red) : PH10
LD2 (green) : PA5
LD3 (blue) : PB9
LD4 (orange) : PD15
ADC1 channel 0 input : PA0
System Clock
STM32H5F5J-DK System Clock could be driven by internal or external oscillator, as well as main PLL clock. By default System clock is driven by PLL clock at 250MHz, driven by 48MHz external oscillator (HSE).
Serial Port
STM32H5F5J-DK Discovery board has 3 U(S)ARTs. The Zephyr console output is assigned to USART2. Default settings are 115200 8N1.
TFT LCD screen and touch panel
The TFT LCD screen and touch panel are supported for the STM32H5F5J-DK Discovery board. They can be tested using LVGL basic sample sample:
# From the root of the zephyr repository
west build -b stm32h5f5j_dk samples/subsys/display/lvgl
Programming and Debugging
The stm32h5f5j_dk board supports the runners and associated west commands listed below.
| flash | debug | attach | debugserver | |
|---|---|---|---|---|
| stlink_gdbserver | ✅ (default) | ✅ | ✅ | |
| stm32cubeprogrammer | ✅ (default) |
STM32H5F5J-DK Discovery board includes an ST-LINK/V3E embedded debug tool interface.
Applications for the stm32h5f5j_dk board configuration can be built and
flashed in the usual way (see Building an Application and
Run an Application for more details).
OpenOCD Support
For now, OpenOCD support for STM32H5 is not available on upstream OpenOCD. You can check OpenOCD official Github mirror. In order to use it though, you should clone from the customized STMicroelectronics OpenOCD Github and compile it following usual README guidelines. Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in boards/st/stm32h5f5j_dk/board.cmake to point the build to the paths of the OpenOCD binary and its scripts, before including the common openocd.board.cmake file:
set(OPENOCD "<path_to_openocd_repo>/src/openocd" CACHE FILEPATH "" FORCE) set(OPENOCD_DEFAULT_PATH <path_to_opneocd_repo>/tcl) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
Flashing
The board is configured to be flashed using west STM32CubeProgrammer runner, so its installation is required.
Application in SoC Flash
Connect the STM32H5F5J-DK Discovery to your host computer using the USB port. Then build and flash an application. Here is an example for the Hello World application.
Run a serial host program to connect with your Nucleo board:
$ minicom -D /dev/ttyACM0
Then build and flash the application.
# From the root of the zephyr repository
west build -b stm32h5f5j_dk samples/hello_world
west flash
You should see the following message on the console:
Hello World! stm32h5f5j_dk/stm32h5f5xx
Debugging
You can debug an application in the usual way. Here is an example for the Hello World application.
# From the root of the zephyr repository
west build -b stm32h5f5j_dk samples/hello_world
west debug